Datasheet

The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0 Register represent special cases when generating a PWM waveform
output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the output will be
continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM
mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in the timing diagram above OCn has a transition from high to low even
though there is no Compare Match. The point of this transition is to guarantee symmetry around
BOTTOM. There are two cases that give a transition without Compare Match:
• OCR0 changes its value from MAX, like in the timing diagram above. When the OCR0 value is MAX the
OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around
BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR0, and for that reason misses the
Compare Match and hence the OCn change that would have happened on the way up.
21.8. Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clk
T0
) is
therefore shown as a clock enable signal. In Asynchronous mode, clk
I/O
should be replaced by the Timer/
Counter Oscillator clock. The figures include information on when Interrupt Flags are set. The following
figure contains timing data for basic Timer/Counter operation. The figure shows the count sequence close
to the MAX value in all modes other than phase correct PWM mode.
Figure 21-8 Timer/Counter Timing Diagram, no Prescaling
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
The next figure shows the same timing data, but with the prescaler enabled.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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