Datasheet

20.11.30. ETIFR – Extended Timer/Counter Interrupt Flag Register
Name: ETIFR
Offset: 0x7C
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
ICF3 OCF3A OCF3B TOV3 OCF3C OCF1C
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 5 – ICF3: Timer/Counter3, Input Capture Flag
This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register (ICR3) is
set by the WGM3:0 to be used as the TOP value, the ICF3 flag is set when the counter reaches the TOP
value.
ICF3 is automatically cleared when the Input Capture 3 interrupt vector is executed. Alternatively, ICF3
can be cleared by writing a logic one to its bit location.
Bit 4 – OCF3A: Timer/Counter3, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare
Register A (OCR3A).
Note that a forced output compare (FOC3A) strobe will not set the OCF3A flag.
OCF3A is automatically cleared when the Output Compare Match 3 A interrupt vector is executed.
Alternatively, OCF3A can be cleared by writing a logic one to its bit location.
Bit 3 – OCF3B: Timer/Counter3, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare
Register B (OCR3B).
Note that a forced output compare (FOC3B) strobe will not set the OCF3B flag.
OCF3B is automatically cleared when the Output Compare Match 3 B interrupt vector is executed.
Alternatively, OCF3B can be cleared by writing a logic one to its bit location.
Bit 2 – TOV3: Timer/Counter3, Overflow Flag
The setting of this flag is dependent of the WGM3:0 bits setting. In normal and CTC modes, the TOV3
flag is set when the timer overflows. Refer to Table 22-2 Waveform Generation Mode Bit Description on
page 226 for the TOV3 flag behavior when using another WGM3:0 bit setting.
TOV3 is automatically cleared when the Timer/Counter3 Overflow interrupt vector is executed.
Alternatively, TOV3 can be cleared by writing a logic one to its bit location.
Bit 1 – OCF3C: Timer/Counter3, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare
Register C (OCR3C).
Note that a forced output compare (FOC3C) strobe will not set the OCF3C flag.
OCF3C is automatically cleared when the Output Compare Match 3 C interrupt vector is executed.
Alternatively, OCF3C can be cleared by writing a logic one to its bit location.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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