Datasheet

20.11.29. TIFR – Timer/Counter Interrupt Flag Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in
this section. The remaining bits are described in their respective timer sections.
Name: TIFR
Offset: 0x36
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x56
Bit 7 6 5 4 3 2 1 0
ICF1 OCF1A OCF1B TOV1
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is
set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the
TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can
be cleared by writing a logic one to its bit location.
Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare
Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed.
Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare
Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed.
Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
Bit 2 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOV1
Flag is set when the timer overflows. Refer to Table 20-5 Waveform Generation Mode Bit Description on
page 161 for the TOV1 Flag behavior when using another WGMn3:0 bit setting.
• TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is
executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
Atmel ATmega64A [DATASHEET]
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