Datasheet

20.11.28. ETIMSK – Extended Timer/Counter Interrupt Mask Register
Note: 1. This register is not available in ATmega103 compatibility mode.
Name: ETIMSK
Offset: 0x7D
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
TICIE3 OCIE3A OCIE3B TOIE3 OCIE3C OCIE1C
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter3 Input Capture Interrupt is enabled. The corresponding interrupt vector (refer to Interrupts
on page 77) is executed when the ICF3 flag, located in ETIFR, is set.
Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter3 Output Compare A Match Interrupt is enabled. The corresponding interrupt vector (refer
to Interrupts on page 77) is executed when the OCF3A flag, located in ETIFR, is set.
Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter3 Output Compare B Match Interrupt is enabled. The corresponding interrupt vector (refer
to Interrupts on page 77) is executed when the OCF3B flag, located in ETIFR, is set.
Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter3 Overflow Interrupt is enabled. The corresponding interrupt vector (refer to Interrupts on
page 77) is executed when the TOV3 flag, located in ETIFR, is set.
Bit 1 – OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter3 Output Compare C Match Interrupt is enabled. The corresponding interrupt vector (refer
to Interrupts on page 77) is executed when the OCF3C flag, located in ETIFR, is set.
Bit 0 – OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare C Match Interrupt is enabled. The corresponding interrupt vector (refer
to Interrupts on page 77) is executed when the OCF1C flag, located in ETIFR, is set.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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