Datasheet

20.11.10. TCNT3H – Timer/Counter3 High byte
Name: TCNT3H
Offset: 0x89
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
TCNT1H[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – TCNT1H[7:0]: Timer/Counter 1 High byte
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both
for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high
and low bytes are read and written simultaneously when the CPU accesses these registers, the access is
performed using an 8-bit temporary High Byte Register (TEMP). This Temporary Register is shared by all
the other 16-bit registers. Refer to Accessing 16-bit Registers for details.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a compare match
between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all
compare units.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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