Datasheet

20.11.6. TCCR3C – Timer/Counter3 Control Register C
Name: TCCR3C
Offset: 0x8C
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
FOC3A FOC3B FOC3C
Access
W W W
Reset 0 0 0
Bit 7 – FOC3A: Force Output Compare for channel A
Bit 6 – FOC3B: Force Output Compare for channel B
Bit 5 – FOC3C: Force Output Compare for channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode.
When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare match is forced on
the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits
setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value
present in the COMnx1:0 bits that determine the effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
Atmel ATmega64A [DATASHEET]
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