Datasheet

20.11.3. TCCR1B – Timer/Counter1 Control Register B
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: TCCR1B
Offset: 0x2E
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x4E
Bit 7 6 5 4 3 2 1 0
ICNC1 ICES1 WGM13 WGM12 CS12 CS11 CS10
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 – ICNC1: Input Capture Noise Canceler
Bit 6 – ICES1: Input Capture Edge Select
Bit 4 – WGM13: Waveform Generation Mode
Bit 3 – WGM12: Waveform Generation Mode
Bits 2:0 – CS1n: Clock Select [n = 0:2]
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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