Datasheet

20.11.2. TCCR3A – Timer/Counter3 Control Register A
Name: TCCR3A
Offset: 0x8B
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x4F
Bit 7 6 5 4 3 2 1 0
COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM11 WGM10
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:6 – COM3An: Compare Output Mode for Channel A [n = 1:0]
Bits 5:4 – COM3Bn: Compare Output Mode for Channel B [n = 1:0]
Bits 3:2 – COM3Cn: Compare Output Mode for Channel C [n = 1:0]
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB, and OCnC
respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides
the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bits are
written to one, the OCnB output overrides the normal port functionality of the I/O pin it is connected to. If
one or both of the COMnC1:0 bits are written to one, the OCnC output overrides the normal port
functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit
corresponding to the OCnA, OCnB or OCnC pin must be set in order to enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent
of the WGMn3:0 bits setting. The table below shows the COMnx1:0 bit functionality when the WGMn3:0
bits are set to a normal or a CTC mode (non-PWM).
Table 20-2 Compare Output Mode, non-PWM
COMnA1/COMnB1/
COMnC1
COMnA0/COMnB0/
COMnC0
Description
0 0 Normal port operation, OCnA/OCnB/OCnC disconnected.
0 1 Toggle OCnA/OCnB/OCnC on compare match.
1 0 Clear OCnA/OCnB/OCnC on compare match (set output to
low level).
1 1 Set OCnA/OCnB/OCnC on compare match (set output to
high level).
The next table shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM
mode.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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