Datasheet

20.11.1. TCCR1A – Timer/Counter1 Control Register A
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: TCCR1A
Offset: 0x2F
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x4F
Bit 7 6 5 4 3 2 1 0
COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:6 – COM1An: Compare Output Mode for Channel A [n = 1:0]
Bits 5:4 – COM1Bn: Compare Output Mode for Channel B [n = 1:0]
Bits 3:2 – COM1Cn: Compare Output Mode for Channel C [n = 1:0]
Bits 1:0 – WGM1n: Waveform Generation Mode [n = 1:0]
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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