Datasheet

The extreme values for the OCRnx Register represent special cases when generating a PWM waveform
output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be
continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode.
For inverted PWM the output will have the opposite logic values.
If OCRnA is used to define the TOP value (WGMn3:0 = 11) and COMnA1:0 = 1, the OCnA output will
toggle with a 50% duty cycle.
20.9.5. Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode
(WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation
option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a
dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP
to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the
Compare Match between TCNTn and OCRnx while upcounting, and set on the Compare Match while
downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation
gives a lower maximum operation frequency compared to the single-slope operation. However, due to the
symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the
time the OCRnx Register is updated by the OCRnx Buffer Register, (refer to Figure 20-8 Phase Correct
PWM Mode, Timing Diagram on page 153 and the timing diagram below).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or
OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum
resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the
following equation:

PFCPWM
=
log TOP+1
log 2
In phase and frequency correct PWM mode the counter is incremented until the counter value matches
either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then
reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer
clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on
timing diagram below. The figure shows phase and frequency correct PWM mode when OCRnA or ICRn
is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the
dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx
Interrupt Flag will be set when a Compare Match occurs.
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
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