Datasheet

Figure 20-8 Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either
OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accordingly at the same
timer clock cycle as the OCRnx Registers are updated with the double buffer value (at TOP). The
Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM
value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the
value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a
Compare Match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP
values, the unused bits are masked to zero when any of the OCRnx Registers are written. As the third
period shown in the timing diagram above illustrates, changing the TOP actively while the Timer/Counter
is running in the Phase Correct mode can result in an unsymmetrical output. The reason for this can be
found in the time of update of the OCRnx Register. Since the OCRnx update occurs at TOP, the PWM
period starts and ends at TOP. This implies that the length of the falling slope is determined by the
previous TOP value, while the length of the rising slope is determined by the new TOP value. When these
two values differ the two slopes of the period will differ in length. The difference in length gives the
unsymmetrical result on the output.
It is recommended to use the Phase and Frequency Correct mode instead of the Phase Correct mode
when changing the TOP value while the Timer/Counter is running. When using a static TOP value there
are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be
generated by setting the COMnx1:0 to 3. Refer to Table 20-4 Compare Output Mode, Phase Correct and
Phase and Frequency Correct PWM on page 160. The actual OCnx value will only be visible on the port
pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by
setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn when the
counter increments, and clearing (or setting) the OCnx Register at Compare Match between OCRnx and
TCNTn when the counter decrements. The PWM frequency for the output when using phase correct
PWM can be calculated by the following equation:

OCnxPCPWM
=

clk_I/O
2    TOP
N variable represents the prescale divider (1, 8, 64, 256, or 1024).
Atmel ATmega64A [DATASHEET]
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