Datasheet

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn

pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to

increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The

output from the clock select logic is referred to as the timer clock (clk

The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter

value at all time. The result of the compare can be used by the waveform generator to generate a PWM

or variable frequency output on the Output Compare Pin (OCnA/B/C). See Output Compare Units on

page 146. The Compare Match event will also set the Compare Match Flag (OCFnA/B/C) which can be

used to generate an Output Compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered)

event on either the Input Capture Pin (ICPn) or on the Analog Comparator pins (see Analog Comparator).

The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of

capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either

the OCRnA Register, the ICRn Register, or by a set of fixed values. When using OCRnA as TOP value in

a PWM mode, the OCRnA Register can not be used for generating a PWM output. However, the TOP

value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP

value is required, the ICRn Register can be used as an alternative, freeing the OCRnA to be used as

PWM output.