Datasheet

TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine.
When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this
pin can not be used as an I/O pin.
• ADC3 – ADC0 – Port F, Bit 3:0
Analog to Digital Converter, Channel 3:0.
Table 18-19 Overriding Signals for Alternate Functions PF7:PF4
Signal
Name
PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK
PUOE JTAGEN JTAGEN JTAGEN JTAGEN
PUOV 1 0 1 1
DDOE JTAGEN JTAGEN JTAGEN JTAGEN
DDOV 0 SHIFT_IR + SHIFT_DR 0 0
PVOE 0 JTAGEN 0 0
PVOV 0 TDO 0 0
DIEOE JTAGEN JTAGEN JTAGEN JTAGEN
DIEOV 0 0 0 0
DI – – – –
AIO TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5 INPUT TCKADC4 INPUT
Table 18-20 Overriding Signals for Alternate Functions in PF3:PF0
Signal
Name
PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE 0 0 0 0
PVOV 0 0 0 0
DIEOE 0 0 0 0
DIEOV 0 0 0 0
DI – – – –
AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT
Atmel ATmega64A [DATASHEET]
Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015
109