ATmega64A ATmega64A DATASHEET COMPLETE Introduction ® The Atmel ATmega64A is a low-power CMOS 8-bit microcontroller based ® on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64A achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed.
• • – Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface Atmel QTouch® library support – Capacitive touch buttons, sliders and wheels – Atmel QTouch and QMatrix acquisition – Up to 64 sense channels Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and Capture Mode – – – – – • • • • Real Time Counter with Separate Oscillator Two 8-bit PWM Channels 6 PWM Channels
Table of Contents Introduction......................................................................................................................1 Features.......................................................................................................................... 1 1. Description.................................................................................................................9 2. Configuration Summary............................................................................
13.3. Default Clock Source..................................................................................................................54 13.4. Crystal Oscillator........................................................................................................................ 54 13.5. Low-frequency Crystal Oscillator................................................................................................55 13.6. External RC Oscillator........................................................
20.1. Features................................................................................................................................... 137 20.2. Overview...................................................................................................................................137 20.3. Accessing 16-bit Registers.......................................................................................................140 20.4. Timer/Counter Clock Sources.........................................
25.2. Overview...................................................................................................................................245 25.3. Clock Generation......................................................................................................................247 25.4. Frame Formats.........................................................................................................................250 25.5. USART Initialization.................................................
29.13. Boundary-scan Chain...............................................................................................................344 29.14. ATmega64A Boundary-scan Order.......................................................................................... 354 29.15. Boundary-scan Description Language Files............................................................................ 363 29.16. Register Description.....................................................................................
34.7. Pin Driver Strength................................................................................................................... 449 34.8. Pin Thresholds and Hysteresis.................................................................................................451 34.9. BOD Thresholds and Analog Comparator Offset..................................................................... 454 34.10. Internal Oscillator Speed............................................................................
1. Description The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
2. Configuration Summary Features ATmega64A Pin count 64 Flash (KB) 64 SRAM (KB) 4 EEPROM (KB) 2 General Purpose I/O pins 53 SPI 1 TWI (I2C) 1 USART 2 ADC 10-bit, up to 76.9ksps (15ksps at max resolution) ADC channels 6 (8 in TQFP and QFN/MLF packages) AC propagation delay Typ 400ns 8-bit Timer/Counters 2 16-bit Timer/Counters 1 PWM channels 8 RC Oscillator +/-3% VREF Bandgap Operating voltage 2.7 - 5.
3. Ordering Information Speed (MHz) 16 Power Supply 2.7 - 5.5V Ordering Code(2) Package(1) ATmega64A-AU ATmega64A-AUR(3) 64A 64A ATmega64A-MU 64M1 ATmega64A-MUR(3) 64M1 ATmega64A-AN ATmega64A-ANR(3) 64A 64A ATmega64A-MN 64M1 ATmega64A-MNR(3) 64M1 Operational Range Industrial (-40oC to 85oC) Extended (-40oC to 105oC)(4) Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
4. Block Diagram Figure 4-1 Block Diagram SRAM TCK TMS TDI TDO JTAG OCD PARPROG PEN PDI PDO SCK CPU FLASH NVM programming EEPROMIF SERPROG ExtMem AD[7:0] A[15:8] RD/WR/ALE I/O PORTS PA[7:0] PB[7:0] PC[7:0] PD[7:0] PE[7:0] PF[7:0] PG[4:0] ExtInt INT[7:0] Clock generation XTAL1 XTAL2 TOSC1 8MHz Crystal Osc 8MHz Calib RC 12MHz External RC Osc External clock 32.
5. ATmega103 and ATmega64A Compatibility The ATmega64A is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATmega64A. Most additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF, (that is, in the ATmega103 internal RAM space).
6.
6.1.2. GND Ground. 6.1.3. Port A (PA7:PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tristated when a reset condition becomes active, even if the clock is not running.
6.1.7. Port E (PE7:PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tristated when a reset condition becomes active, even if the clock is not running.
6.1.11. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 6.1.12. XTAL2 Output from the inverting Oscillator amplifier. 6.1.13. AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 6.1.14. AREF AREF is the analog reference pin for the A/D Converter. 6.1.15.
7. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
8. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
9. About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
10. Capacitive Touch Sensing The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most ® Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller.
11. AVR CPU Core 11.1. Overview This section discusses the Atmel AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.
The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application program section. Both sections have dedicated Lock Bits for write and read/write protection.
11.3.1. SREG – The AVR Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
Bit 0 – C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 11.4. General Purpose Register File The Register File is optimized for the Atmel AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • • • • One 8-bit output operand and one 8-bit result input.
Figure 11-3 The X-, Y- and Z-Registers 15 X-re gis te r XH XL 7 0 7 0 R27 (0x1B) 15 Y-re gis te r R26 (0x1A) YH YL 7 0 Z-re gis te r ZH 7 0 0 7 0 R29 (0x1D) 15 0 R28 (0x1C) ZL 7 0 0 R31 (0x1F) R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details). 11.5.
The following figure shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag.
C Code Example _enable_interrupt(); /* set global interrupt enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ Related Links Memory Programming on page 383 Interrupts on page 77 BTLDR - Boot Loader Support – Read-While-Write Self-Programming on page 366 11.7.1. Interrupt Response Time The interrupt execution response for all the enabled Atmel AVR interrupts is four clock cycles minimum.
12. AVR Memories 12.1. Overview This section describes the different memories in the Atmel AVR ATmega64A. The AVR architecture has two main memory spaces, the Data memory and the Program Memory space. In addition, the ATmega64A features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 12.2. In-System Reprogrammable Flash Program Memory The ATmega64A contains 64K bytes On-chip In-System Reprogrammable Flash memory for program storage.
12.3. SRAM Data Memory The Atmel AVR ATmega64A supports two different configurations for the SRAM data memory as listed in the table below Table 12-1 Memory Configurations Configuration Internal SRAM Data Memory External SRAM Data Memory Normal mode 4096 up to 64K ATmega103 Compatibility mode 4000 up to 64K Figure 12-2 Data Memory Map on page 32 shows how the ATmega64A SRAM Memory is organized.
The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Zregister. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.
Figure 12-3 On-chip Data SRAM Access Cycles T1 T2 T3 clkCP U Addre s s Compute Addre s s Addre s s Va lid Write Da ta WR Re a d Da ta RD Me mory Vcce s s Ins truction 12.4. Next Ins truction EEPROM Data Memory The Atmel AVR ATmega64A contains 2Kbytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down. 12.4.3. Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.
• • 12.6.2. The number of bits dedicated to address high byte is selectable. Bus-keepers on data lines to minimize current consumption (optional). Overview With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCD-display, A/D, and D/A.
12.6.3. ATmega103 Compatibility Both External Memory Control Registers (XMCRA and XMCRB) are placed in Extended I/O space. In ATmega103 compatibility mode, these registers are not available, and the features selected by these registers are not available. The device is still ATmega103 compatible, as these features did not exist in ATmega103. The limitations in ATmega103 compatibility mode are: • • • • • 12.6.4. Only two wait-states settings are available (SRW1n = 0b00 and SRW1n = 0b01).
• Data (address) hold time after G low (TH). The External Memory Interface is designed to guaranty minimum address hold time after G is asserted low of th = 5ns. Refer to tLAXX_LD/tLLAXX_ST in all the tables in section External Data Memory Timing. The D-to-Q propagation delay (tPD) must be taken into consideration when calculating the access time requirement of the external component.
Figure 12-6 External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0) T1 T2 T3 T4 S ys te m Clock (CLKCP U ) ALE A15:8 P rev. a ddr. DA7:0 P rev. da ta Addre s s DA7:0 (XMBK = 0) P rev. da ta Addre s s DA7:0 (XMBK = 1) P rev. da ta Addre s s Addre s s XX Write Da ta WR Da ta XXXXX XXXXXXXX Re a d Da ta RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
Figure 12-8 External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1) T1 T2 T3 T4 T5 T6 S ys te m Clock (CLKCP U ) ALE A15:8 P rev. a ddr. DA7:0 P rev. da ta Addre s s DA7:0 (XMBK = 0) P rev. da ta Addre s s DA7:0 (XMBK = 1) P rev. da ta Addre s s Write Da ta XX WR Addre s s Re a d Da ta Da ta RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
to 0x90FF. This is illustrated in the figure below. Memory configuration B refers to the ATmega103 compatibility mode, configuration A to the non-compatible mode. When the device is set in Atmel AVR ATmega103 compatibility mode, the internal address space is 4,096 bytes. This implies that the first 4,096 bytes of the external memory can be accessed at addresses 0x8000 to 0x8FFF.
ldi r16, (1<
12.7.1. EEARL – The EEPROM Address Register Low When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
12.7.2. EEARH – The EEPROM Address Register High When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
12.7.3. EEDR – The EEPROM Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
12.7.4. EECR – The EEPROM Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.
C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
12.7.5. MCUCR – MCU Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
12.7.6. XMCRA – External Memory Control Register A Name: XMCRA Offset: 0x6D Reset: 0x00 Property: – Bit 7 Access Reset 6 5 4 3 2 1 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 6:4 – SRLn: Wait-state Sector Limit [n = 2:0] It is possible to configure different wait-states for different External Memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits.
Table 12-4 Wait States(1) SRWn1 SRWn0 Wait States 0 0 No wait-states 0 1 Wait one cycle during read/write strobe 1 0 Wait two cycles during read/write strobe 1 1 Wait two cycles during read/write and wait one cycle before driving out new address Note: 1. n = 0 or 1 (lower/upper sector). For further details of the timing and wait-states of the External Memory Interface, see Figures 13-6 through Figures 13-9 for how the setting of the SRW bits affects the timing.
12.7.7. XMCRB – External Memory Control Register B Name: XMCRB Offset: 0x6C Reset: 0x00 Property: – Bit 7 Access Reset 2 1 0 XMBK 6 5 4 3 XMM2 XMM1 XMM0 R/W R/W R/W R/W 0 0 0 0 Bit 7 – XMBK: External Memory Bus-keeper Enable Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise be tri-stated. Writing XMBK to zero disables the bus keeper.
13. 13.1. System Clock and Clock Options Clock Systems and their Distribution The figure below presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in Power Management and Sleep Modes on page 61. The clock systems are detailed in the following figure.
13.1.3. Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 13.1.4. Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 13.1.5.
13.3. Default Clock Source The device is shipped with CKSEL = “0001” and SUT = “10”. The default clock source setting is therefore the Internal RC Oscillator with longest startup time. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel Programmer. 13.4. Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in the figure below.
The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in the next table. Table 13-4 Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1:0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) Recommended Usage 0 00 258 CK(1) 4.1ms Ceramic resonator, fast rising power 0 01 258 CK(1) 65ms Ceramic resonator, slowly rising power 0 10 1K CK(2) – Ceramic resonator, BOD enabled 0 11 1K CK(2) 4.
13.6. External RC Oscillator For timing insensitive applications, the external RC configuration shown in the figure below can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22pF. By programming the CKOPT Fuse, the user can enable an internal 36pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor.
The CKOPT Fuse should always be unprogrammed when using this clock option. During reset, hardware loads the 1MHz calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 5V, 25°C and 1.0MHz Oscillator frequency selected, this calibration gives a frequency within ± 3% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 1% accuracy at any given VCC and Temperature.
Figure 13-4 External Clock Drive Configuration EXTERNAL CLOCK S IGNAL When this clock source is selected, start-up times are determined by the SUT Fuses as shown in the following table. Table 13-10 Start-up Times for the External Clock Selection SUT1:0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) Recommended Usage 00 6 CK – BOD enabled 01 6 CK 4.
13.10.1. XDIV – XTAL Divide Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
13.10.2. OSCCAL – The Oscillator Calibration Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
14. 14.1. Power Management and Sleep Modes Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. Figure Clock Distribution in section Clock Systems and their Distribution presents the different clock systems in the ATmega64A, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
14.2. Idle Mode When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
• If Timer/Counter0 is clocked asynchronously, i.e. the AS0 bit in ASSR is set, Timer/Counter0 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in TIMSK, and the global interrupt enable bit in SREG is set.
Analog Comparator on page 306 14.8.3. Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brownout Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Brown-out Detection for details on how to configure the Brown-out Detector. Related Links Brown-out Detection on page 70 14.8.
consumption will increase. Note that the TDI pin for the next device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. 14.9.
14.9.1. MCUCR – MCU Control Register The MCU Control Register contains control bits for power management. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
15. System Control and Reset 15.1. Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the boot section or vice versa.
Figure 15-1 Reset Logic DATA BUS D Q L Q MCU Control a nd S ta tus Re gis te r (MCUCS R) P ORF BORF EXTRF WDRF J TRF P EN P ull-up Re s is tor P owe r-On Re s e t Circuit Brown-Out Re s e t Circuit BODEN BODLEVEL P ull-up Re s is tor S P IKE FILTER J TAG Re s e t Re gis te r Re s e t Circuit COUNTER RES ET RES ET Wa tchdog Time r Wa tchdog Os cilla tor Clock Ge ne ra tor CK De la y Counte rs TIMEOUT CKS EL[3:0] S UT[1:0] Related Links IEEE 1149.1 (JTAG) Boundary-scan on page 340 15.2.1.
Figure 15-2 MCU Start-up, RESET Tied to VCC VCC RES ET VP OT VRS T tTOUT TIME-OUT INTERNAL RES ET Figure 15-3 Figure: MCU Start-up, RESET Extended Externally VCC VP OT RES ET TIME-OUT VRS T tTOUT INTERNAL RES ET Related Links System and Reset Characteristics on page 418 15.2.2. External Reset An External Reset is generated by a low level on the RESET pin.
15.2.3. Brown-out Detection ATmega64A has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
15.3. Internal Voltage Reference ATmega64A features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. 15.3.1. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in the table in System and Reset Characteristics.
M103C WDTON Safety Level WDT Initial State How to Disable the WDT How to Change Timeout Programmed Unprogrammed 0 Disabled Timed sequence No restriction Programmed Programmed 2 Enabled Always enabled Timed sequence Figure 15-7 Watchdog Timer WATCHDOG OS CILLATOR 15.5. Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the three safety levels. Separate procedures are described for each level. 15.5.1.
1. 2. 15.6. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
15.6.1. MCUCSR – MCU Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
15.6.2. WDTCR – Watchdog Timer Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
WDP2 WDP1 WDP0 Number of WDT Oscillator Typical Cycles Time-out at VCC = 3.0V Typical Time-out at VCC = 5.0V 1 0 0 256K (262,144) 0.27s 0.26s 1 0 1 512K (524,288) 0.55s 0.52s 1 1 0 1,024K (1,048,576) 1.1s 1.0s 1 1 1 2,048K (2,097,152) 2.2s 2.1s The following code example shows one assembly and one C function for turning off the WDT.
16. Interrupts This section describes the specifics of the interrupt handling performed by the ATmega64A. For a general explanation of the AVR interrupt handling, refer to Reset and Interrupt Handling. Related Links Reset and Interrupt Handling on page 27 16.1. Interrupt Vectors in ATmega64A Table 16-1 Reset and Interrupt Vectors Vector No.
Vector No.
address Labels Code Comments $0000 jmp RESET ; Reset Handler $0002 jmp EXT_INT0 ; IRQ0 Handler $0004 jmp EXT_INT1 ; IRQ1 Handler $0006 jmp EXT_INT2 ; IRQ2 Handler $0008 jmp EXT_INT3 ; IRQ3 Handler $000A jmp EXT_INT4 ; IRQ4 Handler $000C jmp EXT_INT5 ; IRQ5 Handler $000E jmp EXT_INT6 ; IRQ6 Handler $0010 jmp EXT_INT7 ; IRQ7 Handler $0012 jmp TIM2_COMP ; Timer2 Compare Handler $0014 jmp TIM2_OVF ; Timer2 Overflow Handler $0016 jmp TIM1_CAPT ; Timer1 Capture H
address Labels Code Comments $002E jmp ANA_COMP ; Analog Comparator Handler $0030 jmp TIM1_COMPC ; Timer1 CompareC Handler $0032 jmp TIM3_CAPT ; Timer3 Capture Handler $0034 jmp TIM3_COMPA ; Timer3 CompareA Handler $0036 jmp TIM3_COMPB ; Timer3 CompareB Handler $0038 jmp TIM3_COMPC ; Timer3 CompareC Handler $003A jmp TIM3_OVF ; Timer3 Overflow Handler $003C jmp USART1_RXC ; USART1 RX Complete Handler $003E jmp USART1_DRE ; USART1,UDR Empty Handler $0040 jmp USART1_T
When the BOOTRST fuse is unprogrammed, the Boot section size set to 8 Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Adddress Labels Code $0000 RESET: ldi r16,high(RAMEND) ; Main program start out SPH,r16 ; Set stack pointer to top of RAM ldi r16,low(RAMEND) $0003 out SPL,r16 $0004 sei $0005 xxx $F002 jmp EXT_INT0 ; IRQ0 Handler $F004 jmp EX
Address Labels Code Comments $F002 ldi r16,low(RAMEND) $F003 out SPL,r16 $F004 sei $F005 ; Enable interrupts xxx When the BOOTRST fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments ; .
16.2.1. MCUCR – MCU Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<
17. External Interrupts The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0) and EICRB (INT7:4).
17.1.1. EICRA – External Interrupt Control Register A This Register can not be reached in ATmega103 compatibility mode, but the initial value defines INT3:0 as low level interrupts, as in ATmega103.
Bits 3:2 – ISC1n: External Interrupt 1 Sense Control Bits [n = 1:0] Refer to ISC3n bit description above. Bits 1:0 – ISC0n: External Interrupt 0 Sense Control Bits [n = 1:0] Refer to ISC3n bit description above.
17.1.2. EICRB – External Interrupt Control Register B When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
Bits 1:0 – ISC4n: External Interrupt 4 Sense Control Bits [n = 1:0] Refer to ISC7n bit description above.
17.1.3. EIMSK – External Interrupt Mask Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
17.1.4. EIFR – External Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18. I/O Ports 18.1. Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Electrical Characteristics – TA = -40°C to 85°C on page 415 18.2. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. The following figure shows a functional description of one I/O-port pin, here generically called Pxn.
PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem.
tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1-½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in the figure below. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
C Code Example(1) unsigned char i; :. /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<
Figure 18-5 Alternate Port Functions(1) PUOExn 1 PUOVxn PUD 0 DDOExn 1 DDOVxn Q D DDxn 0 Q CLR PVOExn RESET WDx RDx 1 Pxn Q 0 D PORTxn Q CLR DIEOExn 1 0 WPx DIEOVxn DATA BUS PVOVxn RESET RRx SLEEP SYNCHRONIZER D SET Q D RPx Q PINxn L CLR Q CLR Q clk I/O DIxn AIOxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PUD: Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn POR
Signal Name Full Name Description DDOE Data Direction Override Enable If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. DDOV Data Direction Override Value If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.
The two tables below relates the alternate functions of Port A to the overriding signals shown in the figure in section Alternate Port Functions on page 96.
18.3.2.
• MOSI – Port B, Bit 2 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. • SCK – Port B, Bit 1 SCK: Master Clock output, Slave Clock input pin for SPI channel.
Signal Name PB3/MISO PB2/MOSI PB1/SCK PB0/SS DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR DDOV 0 0 0 0 PVOE SPE • MSTR SPE • MSTR SPE • MSTR 0 PVOV SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI SPI MSTR INPUT SPI SLAVE INPUT SCK INPUT SPI SS AIO – – – – Related Links Output Compare Modulator (OCM1C2) on page 233 18.3.3. Alternate Functions of Port C In ATmega103 compatibility mode, Port C is output only.
Signal Name PC7/A15 PC6/A14 PC5/A13 PC4/A12 DDOV 1 1 1 1 PVOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4) PVOV A15 A14 A13 A12 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO – – – – Note: 1. XMM = 0 in ATmega103 compatibility mode.
Port Pin Alternate Function PD2 INT2/RXD1(1) (External Interrupt2 Input or UART1 Receive Pin) PD1 INT1/SDA(1) (External Interrupt1 Input or TWI Serial Data) PD0 INT0/SCL(1) (External Interrupt0 Input or TWI Serial Clock) Note: 1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode. The alternate pin configuration is as follows: • T2 – Port D, Bit 7 T2, Timer/Counter2 counter source. • T1 – Port D, Bit 6 T1, Timer/Counter1 counter source.
The tables below relate the alternate functions of Port D to the overriding signals shown in the figure in section Alternate Port Functions on page 96.
Table 18-15 Port E Pins Alternate Functions Port Pin Alternate Function PE7 INT7/ICP3(1) (External Interrupt 7 Input or Timer/Counter3 Input Capture Pin) PE6 INT6/ T3(1) (External Interrupt 6 Input or Timer/Counter3 Clock Input) PE5 INT5/OC3C(1) (External Interrupt 5 Input or Output Compare and PWM Output C for Timer/ Counter3) PE4 INT4/OC3B(1) (External Interrupt4 Input or Output Compare and PWM Output B for Timer/ Counter3) PE3 AIN1/OC3A (1) (Analog Comparator Negative Input or Output Compare
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode. • PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega64A.
Signal Name PE3/AIN1/OC3A PE2/AIN0/XCK0 PE1/PDO/TXD0 PE0/PDI/RXD0 PVOE OC3B ENABLE UMSEL0 TXEN0 0 PVOV OC3B XCK0 OUTPUT TXD0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI 0 XCK0 INPUT – RXD0 AIO AIN1 INPUT AIN0 INPUT – – 18.3.6. Alternate Functions of Port F The Port F pins with alternate functions are shown in the table below. If some Port F pins are configured as outputs, it is essential that these do not switch when a conversion is in progress.
TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TCK, ADC4 – Port F, Bit 4 ADC4, Analog to Digital Converter, Channel 4. TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • ADC3 – ADC0 – Port F, Bit 3:0 Analog to Digital Converter, Channel 3:0.
18.3.7. Alternate Functions of Port G In ATmega103 compatibility mode, only the alternate functions are the defaults for Port G, and Port G cannot be used as General Digital Port Pins.
Signal Name PG4/TOSC1 PG3/TOSC2 PG2/ALE PG1/RD DIEOE AS0 AS0 0 0 DIEOV 0 0 0 0 DI – – – – AIO T/C0 OSC INPUT T/C0 OSC OUTPUT – – Table 18-23 Overriding Signals for Alternate Functions in PG0 Signal Name PG0/WR PUOE SRE PUOV 0 DDOE SRE DDOV 1 PVOE SRE PVOV WR DIEOE 0 DIEOV 0 DI – AIO – 18.4.
18.4.1. SFIOR – Special Function IO Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.2. PORTA – Port A Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.3. DDRA – Port A Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.4. PINA – Port A Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.5. PORTB – The Port B Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.6. DDRB – The Port B Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.7. PINB – The Port B Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.8. PORTC – The Port C Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.9. DDRC – The Port C Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.10. PINC – The Port C Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.11. PORTD – The Port D Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.12. DDRD – The Port D Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.13. PIND – The Port D Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.14. PORTE – The Port E Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.15. DDRE – The Port E Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.16. PINE – The Port E Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.17.
18.4.18.
18.4.19. PINF – The Port F Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
18.4.20.
18.4.21.
18.4.22. PING – The Port G Input Pins Address Note: PORTG and DDRG Registers are not available in ATmega103 compatibility mode where Port G serves as digital input only.
19. Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers 19.1. Overview Timer/Counter3, Timer/Counter2, and Timer/Counter1 share the same prescaler module, but the Timer/ Counters can have different prescaler settings. The description below applies to Timer/Counter3, Timer/ Counter2, and Timer/Counter1. 19.2. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T3/T2/T1 pin to the counter is updated. Enabling and disabling of the clock input must be done when T3/T2/T1 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling.
19.5.1. SFIOR – Special Function IO Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) 20.1. Features • • • • • • • • • • • True 16-bit Design (i.e.
Figure 20-1 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCFnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCFnB (Int.Req.) Fixed TOP Values Waveform Generation = OCnB OCRnB OCFnC (Int.Req.) Waveform Generation = OCnC ( From Analog Comparator Ouput ) OCRnC ICFn (Int.Req.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkTn). The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter value at all time.
• • Timer/Counter Control Register C (TCCRnC). Output Compare Register C, OCRnCH and OCRnCL, combined OCRnC. The following bits are added to the 16-bit Timer/Counter Control Registers: • • • COM1C1:0 are added to TCCR1A. FOCnA, FOCnB, and FOCnC are added in the new TCCRnC Register. WGMn3 is added to TCCRnB. Interrupt flag and mask bits for output compare unit C are added. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. 20.3.
Note: 1. See About Code Examples. The assembly code example returns the TCNTn value in the r17:r16 Register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted.
out TCNTnL,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNTn( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNTn to i */ TCNTn = i; /* Restore global interrupt flag */ SREG = sreg; } Note: 1. See About Code Examples. The assembly code example requires that the r17:r16 Register pair contains the value to be written to TCNTn.
Figure 20-2 Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) Clear Direction Control Logic clkTn Edge Detector Tn ( From Prescaler ) TOP BOTTOM Signal description (internal signals): count Increment or decrement TCNTn by 1. direction Select between increment and decrement. clear Clear TCNTn (set all bits to zero). clkTn Timer/Counter clock. TOP Signalize that TCNTn has reached maximum value.
be applied via the ICPn pin or alternatively, for the Timer/Counter1 only, via the Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram below. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded.
For more information on how to access the 16-bit registers refer to Accessing 16-bit Registers on page 140. 20.6.1. Input Capture Pin Source The main trigger source for the Input Capture unit is the Input Capture Pin (ICPn). Timer/Counter 1 can alternatively use the Analog Comparator Output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR).
20.7. Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Compare Flag generates an Output Compare interrupt. The OCFnx Flag is automatically cleared when the interrupt is executed.
will access the OCRnx directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNTn and ICRn Register). Therefore OCRnx is not read via the High byte temporary register (TEMP). However, it is a good practice to read the Low byte first as when accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Register since the compare of all 16-bit is done continuously.
Figure 20-5 Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OCnx) from the waveform generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
control whether the output should be set, cleared or toggle at a Compare Match. See Compare Match Output Unit on page 147. For detailed timing information refer to Timer/Counter Timing Diagrams on page 156. 20.9.1. Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed.
use the fast PWM mode using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered. For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCnA = 1).
Figure 20-7 Fast PWM Mode, Timing Diagram OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value.
N represents the prescale divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COMnx1:0 bits.
Figure 20-8 Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM.
The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCRnA is used to define the TOP value (WGMn3:0 = 11) and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle. 20.9.5.
Figure 20-9 Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle. 20.10. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures.
Figure 20-12 Timer/Counter Timing Diagram, no Prescaling. clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM TOP - 1 TOP TOP - 1 BOTTOM + 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) New OCRnx Value Old OCRnx Value The next figure shows the same timing data, but with the prescaler enabled.
20.11.1. TCCR1A – Timer/Counter1 Control Register A When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.2.
Table 20-3 Compare Output Mode, Fast PWM COMnA1/ COMnB1/ COMnC1 COMnA0/ COMnB0/ COMnC0 Description 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 0 1 WGMn3:0 = 15: Toggle OCnA on Compare Match, OCnB/OCnC disconnected (normal port operation). For all other WGMn settings, normal port operation, OCnA/OCnB/OCnC disconnected.
Table 20-5 Waveform Generation Mode Bit Description Mode WGMn3 WGMn2 WGMn1 WGMn0 Timer/Counter Mode of Operation(1) (CTCn) (PWMn1) (PWMn0) TOP Update of TOVn Flag OCRnx at Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCRnA Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF
20.11.3. TCCR1B – Timer/Counter1 Control Register B When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.4. TCCR3B – Timer/Counter3 Control Register B Name: TCCR3B Offset: 0x8A Reset: 0x00 Property: – Bit Access 7 6 4 3 2 1 0 ICNC3 ICES3 WGM33 WGM32 CS32 CS31 CS30 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Reset 5 Bit 7 – ICNC3: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICPn) is filtered.
CA12 CA11 CS10 Description 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on Tn pin. Clock on falling edge. 1 1 1 External clock source on Tn pin. Clock on rising edge. If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.
20.11.5.
20.11.6. TCCR3C – Timer/Counter3 Control Register C Name: TCCR3C Offset: 0x8C Reset: 0x00 Property: – Bit 7 6 5 FOC3A FOC3B FOC3C Access W W W Reset 0 0 0 4 3 2 1 0 Bit 7 – FOC3A: Force Output Compare for channel A Bit 6 – FOC3B: Force Output Compare for channel B Bit 5 – FOC3C: Force Output Compare for channel C The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode.
20.11.7. TCNT1L – Timer/Counter1 Low byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.8. TCNT1H – Timer/Counter1 High byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.9. TCNT3L – Timer/Counter3 Low byte Name: TCNT3L Offset: 0x88 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 TCNT3L[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TCNT3L[7:0]: Timer/Counter 3 Low byte Refer to TCNT3H.
20.11.10. TCNT3H – Timer/Counter3 High byte Name: TCNT3H Offset: 0x89 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 TCNT1H[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TCNT1H[7:0]: Timer/Counter 1 High byte The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter.
20.11.11. OCR1AL – Output Compare Register 1 A Low byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.12. OCR1AH – Output Compare Register 1 A High byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.13. OCR1BL – Output Compare Register 1 B Low byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.14. OCR1BH – Output Compare Register 1 B High byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.15. OCR1CL – Output Compare Register 1 C Low byte Name: OCR1CL Offset: 0x78 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 OCR1CL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR1CL[7:0]: Output Compare 1 C Low byte Refer to OCR3CH on page 182.
20.11.16. OCR1CH – Output Compare Register 1 C High byte Name: OCR1CH Offset: 0x79 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 OCR1CH[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR1CH[7:0]: Output Compare 1 C High byte Refer to OCR3CH on page 182.
20.11.17. OCR3AL – Output Compare Register 3 A Low byte Name: OCR3AL Offset: 0x86 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 OCR3AL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR3AL[7:0]: Output Compare 3 A Low byte Refer to OCR3CH on page 182.
20.11.18. OCR3AH – Output Compare Register 3 A High byte Name: OCR3AH Offset: 0x87 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 OCR1AH[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR1AH[7:0]: Output Compare 3 A High byte Refer to OCR3CH on page 182.
20.11.19. OCR3BL – Output Compare Register 3 B Low byte Name: OCR3BL Offset: 0x84 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 OCR3BL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR3BL[7:0]: Output Compare 3 B Low byte Refer to OCR3CH on page 182.
20.11.20. OCR3BH – Output Compare Register 3 B High byte Name: OCR3BH Offset: 0x85 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 OCR3BH[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR3BH[7:0]: Output Compare 3 B High byte Refer to OCR3CH on page 182.
20.11.21. OCR3CL – Output Compare Register 3 C Low byte Name: OCR3CL Offset: 0x82 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 OCR3CL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR3CL[7:0]: Output Compare 3 C Low byte Refer to OCR3CH on page 182.
20.11.22. OCR3CH – Output Compare Register 3 C High byte Name: OCR3CH Offset: 0x83 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 OCR3CH[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR3CH[7:0]: Output Compare 3 C High byte The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator Output for Timer/Counter1).
20.11.23. ICR1L – Input Capture Register 1 Low byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.24. ICR1H – Input Capture Register 1 High byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.25. ICR3L – Input Capture Register 3 Low byte Name: ICR3L Offset: 0x80 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 ICR3L[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – ICR3L[7:0]: Input Capture 3 Low byte Refer to ICR3H on page 186.
20.11.26. ICR3H – Input Capture Register 3 High byte Name: ICR3H Offset: 0x81 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 ICR3H[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – ICR3H[7:0]: Input Capture 3 High byte The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
20.11.27. TIMSK – Timer/Counter Interrupt Mask Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.28. ETIMSK – Extended Timer/Counter Interrupt Mask Register Note: 1. This register is not available in ATmega103 compatibility mode.
20.11.29. TIFR – Timer/Counter Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
20.11.30. ETIFR – Extended Timer/Counter Interrupt Flag Register Name: ETIFR Offset: 0x7C Reset: 0x00 Property: – Bit Access Reset 7 6 5 4 3 2 1 0 ICF3 OCF3A OCF3B TOV3 OCF3C OCF1C R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bit 5 – ICF3: Timer/Counter3, Input Capture Flag This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register (ICR3) is set by the WGM3:0 to be used as the TOP value, the ICF3 flag is set when the counter reaches the TOP value.
Bit 0 – OCF1C: Timer/Counter1, Output Compare C Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register C (OCR1C). Note that a forced output compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C interrupt vector is executed. Alternatively, OCF1C can be cleared by writing a logic one to its bit location.
21. 8-bit Timer/Counter0 with PWM and Asynchronous Operation 21.1. Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) • Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock Overview Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module.
21.2.1. Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin.
Figure 21-2 Counter Unit Block Diagram TOVn (Int. Re q.) DATA BUS TOS C1 count TCNTn cle a r Control Logic clk Tn T/C Os cilla tor P re s ca le r dire ction BOTTOM TOS C2 TOP clkI/O Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Selects between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkT0 Timer/Counter clock. TOP Signalizes that TCNT0 has reached maximum value.
Figure 21-3 Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Compa ra tor ) OCFn (Int. Re q.) TOP BOTTOM Wave form Ge ne ra tor OCxy FOCn WGMn1:0 COMn1:0 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence.
Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. The setup of the OC0 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0 value is to use the Force Output Compare (FOC0) strobe bit in Normal mode. The OC0 Register keeps its value even when changing between waveform generation modes.
The design of the Output Compare Pin logic allows initialization of the OC0 state before the output is enabled. Note that some COM01:0 bit settings are reserved for certain modes of operation. See Register Description. 21.6.1. Compare Output Mode and Waveform Generation The Waveform Generator uses the COM01:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM01:0 = 0 tells the waveform generator that no action on the OC0 Register is to be performed on the next Compare Match.
Figure 21-5 CTC Mode, Timing Diagram OCn Inte rrupt Fla g S e t TCNTn OCn (Toggle ) Pe riod (COMn1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. Figure 21-6 Fast PWM Mode, Timing Diagram OCRn Inte rrupt Fla g S e t OCRn Upda te a nd TOVn Inte rrupt Fla g S e t TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Pe riod 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
21.7.4. Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0 while upcounting, and set on the Compare Match while downcounting.
The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
Figure 21-9 Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn The next figure shows the setting of OCF0 in all modes except CTC mode. Figure 21-10 Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Va lue OCFn The figure below shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.
21.9. Asynchronous Operation of the Timer/Counter 21.9.1. Asynchronous Operation of Timer/Counter0 When Timer/Counter0 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter0, the Timer Registers TCNT0, OCR0, and TCCR0 might be corrupted. A safe procedure for switching clock source is: 1. 2. 3. 4. 5. 6. Disable the Timer/Counter0 interrupts by clearing OCIE0 and TOIE0.
• or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. Description of wake up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value.
and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter0. The Oscillator is optimized for use with a 32.768kHz crystal. Applying an external clock source to TOSC1 is not recommended. For Timer/Counter0, the possible prescaled selections are: clkT0S/8, clkT0S/32, clkT0S/64, clkT0S/128, clkT0S/256, and clkT0S/1024. Additionally, clkT0S as well as 0 (stop) may be selected.
21.11.1. TCCR0 – Timer/Counter Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
Table 21-4 Compare Output Mode, Fast PWM Mode(1) COM01 COM00 Description 0 0 Normal port operation, OC0 disconnected. 0 1 Reserved 1 0 Clear OC0 on Compare Match, set OC0 at BOTTOM, (non-inverting mode) 1 1 Set OC0 on Compare Match, clear OC0 at BOTTOM, (inverting mode) Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode on page 198 for more details.
If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. Bits 6,3 – WGM0n: Waveform Generation Mode [n=0:1] These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used.
21.11.2. TCNT0 – Timer/Counter Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
21.11.3. OCR0 – Output Compare Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
21.11.4. ASSR – Asynchronous Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
21.11.5. TIMSK – Timer/Counter Interrupt Mask Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
21.11.6. TIFR – Timer/Counter Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
21.11.7. SFIOR – Special Function IO Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
22. 8-bit Timer/Counter2 with PWM 22.1. Features • • • • • • • Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in the figure below. For the actual placement of I/O pins, refer to Pin Configurations. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Register Description on page 225.
22.2.1. Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units.
Figure 22-2 Counter Unit Block Diagram TOVn (Int. Re q.) DATA BUS Clock Select Edge Detector count TCNTn cle a r Control Logic Tn dire ction (From Prescaler) BOTTOM TOP Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkT2 Timer/Counter clock. TOP Signalizes that TCNT2 has reached maximum value. BOTTOM Signalizes that TCNT2 has reached minimum value (zero).
Figure 22-3 Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Compa ra tor ) OCFn (Int. Re q.) TOP BOTTOM Wave form Ge ne ra tor OCn FOCn WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence.
22.6. Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin output source. The figure below shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
A change of the COM21:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2 strobe bits. 22.7. Modes of Operation The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits.
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
Figure 22-6 Fast PWM Mode, Timing Diagram OCRn Inte rrupt Fla g S e t OCRn Upda te a nd TOVn Inte rrupt Fla g S e t TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Pe riod 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin.
upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX.
continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in the timing diagram OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without a Compare Match: • OCR2 changes its value from MAX, like in the timing diagram above.
Figure 22-10 Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Va lue OCFn The next figure shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 22-11 Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) OCRn TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCFn 22.9.
22.9.1. TCCR2 – Timer/Counter Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
Bits 5:4 – COM2n: Compare Match Output Mode [n = 1:0] These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting.
Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See Phase Correct PWM Mode on page 222 for more details. Bit 3 – WGM21: Waveform Generation Mode [n=0:1] Refer to WGM20 above. Bits 2:0 – CS2n: Clock Select [n = 2:0] The three Clock Select bits select the clock source to be used by the Timer/Counter.
22.9.2. TCNT0 – Timer/Counter Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
22.9.3. OCR0 – Output Compare Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
22.9.4. TIMSK – Timer/Counter Interrupt Mask Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
22.9.5. TIFR – Timer/Counter Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
23. Output Compare Modulator (OCM1C2) 23.1. Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter2. For more details about these Timer/Counters see 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) and 8-bit Timer/Counter2 with PWM.
Figure 23-2 Output Compare Modulator, Schematic COM21 COM20 Vcc COM1C1 COM1C0 ( From Waveform Generator ) Modulator 0 D 1 Q 1 OC1C Pin 0 ( From Waveform Generator ) D OC1C / OC2 / PB7 Q OC2 D Q D PORTB7 Q DDRB7 DATABUS When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. 23.2.1.
24. SPI – Serial Peripheral Interface 24.1. Features Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • • • • End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega64A and peripheral devices or between several AVR devices.
The interconnection between Master and Slave CPUs with SPI is shown in the figure below. The system consists of two shift registers, and a Master Clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
Table 24-1 SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. Refer to table Port B Pins Alternate Functions in Alternate Functions of Port B for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
Note: 1. See About Code Examples. The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
the SPI is passive, which means that it will not receive incoming data. The SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 24.3.2.
Figure 24-3 SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 24-4 SPI Transfer Format with CPHA = 1 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) 24.5.
24.5.1. SPCR – SPI Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
Table 24-4 CPHA Functionality CPHA Leading Edge Trailing Edge 0 Sample Setup 1 Setup Sample Bits 1:0 – SPRn: SPI Clock Rate Select [n = 1:0] These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the table below.
24.5.2. SPSR – SPI Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
24.5.3. SPDR – SPI Data Register is a read/write register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
25. USART 25.1. Features • • • • • • • • • • • • 25.1.1.
Figure 25-1 USART Block Diagram(1) Clock Generator UBRRn [H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCKn Transmitter TX CONTROL DATA BUS UDRn(Transmit) PARITY GENERATOR PIN CONTROL TRANSMIT SHIFT REGISTER TxDn Receiver CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDRn (Receive) PARITY CHECKER UCSRnA UCSRnB RxDn UCSRnC Note: 1.
25.2.1. AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • • • • • Bit locations inside all USART Registers. Baud Rate Generation. Transmitter Operation. Transmit Buffer Functionality. Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer.
Figure 25-2 Clock Generation Logic, Block Diagram UBRRn U2Xn foscn Prescaling Down-Counter UBRRn+1 /2 /4 /2 0 1 0 OSC DDR_XCKn xcki XCKn Pin Sync Register Edge Detector xcko DDR_XCKn 1 0 UMSELn 1 UCPOLn txclk 1 0 rxclk Signal description: 25.3.1. txclk Transmitter clock (internal signal). rxclk Receiver base clock (internal signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (internal signal).
Table 25-1 Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal mode (U2X = 0) Asynchronous Double Speed mode (U2X = 1) Synchronous Master mode Equation for Calculating Baud Rate(1) BAUD = BAUD = BAUD = Equation for Calculating UBRR Value �OSC 16 ���� + 1 ���� = �OSC 2 ����+1 ���� = �OSC 8 ���� + 1 ���� = �OSC −1 16BAUD �OSC −1 8BAUD �OSC −1 2BAUD Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).
Figure 25-3 Synchronous Mode XCK Timing UCPOL = 1 XCK RxD / TxD Sample UCPOL = 0 XCK RxD / TxD Sample The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As the figure above shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. 25.4.
The USART Character Size (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop bit is zero 25.4.1. Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits.
C Code Example(1) #define FOSC 1843200 // Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) { :. USART_Init(MYUBRR); :. } void USART_Init( unsigned int ubrr) { /*Set baud rate */ UBRRH = (unsigned char)(ubrr>>8); UBRRL = (unsigned char)ubrr; Enable receiver and transmitter */ UCSRB = (1<
Assembly Code Example(1) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRA,UDRE rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR,r16 ret C Code Example(1) void USART_Transmit( unsigned char data ) { /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<
} UCSRB &= ~(1<
25.7. Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock. 25.7.1.
receive buffer FIFO and consequently the TXB8, FE, DOR, and UPE bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both 9-bit characters and the status bits.
does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero. When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete Interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled).
25.7.7. Flushing the Receive Buffer The Receiver buffer FIFO will be flushed when the Receiver is disabled (i.e., the buffer will be emptied of its contents). Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is cleared. The following code example shows how to flush the receive buffer.
Figure 25-5 Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in the figure above. For Double Speed mode the first low level must be delayed to (B).
Table 25-3 Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) D # (Data+Parity Bit) Rslow [%] Rfast [%] Max Total Error [%] Recommended Max Receiver Error [%] 5 94.12 105.66 +5.66/-5.88 ±2.5 6 94.92 104.92 +4.92/-5.08 ±2.0 7 95.52 104.35 +4.35/-4.48 ±1.5 8 96.00 103.90 +3.90/-4.00 ±1.5 9 96.39 103.53 +3.53/-3.61 ±1.5 10 96.70 103.23 +3.23/-3.30 ±1.
2. 3. 4. 5. The Master MCU sends an address frame, and all slaves receive and read this frame. In the Slave MCUs, the RXC Flag in UCSRA will be set as normal. Each Slave MCU reads the UDR Register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte and keeps the MPCM setting. The addressed MCU will receive all data frames until a new address frame is received.
Baud Rate [bps] fosc = 1.0000MHz U2X = 0 fosc = 1.8432MHz U2X = 1 U2X= 0 fosc = 2.0000MHz U2X = 1 U2X = 0 U2X = 1 UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k – – – – – – 0 0.0% – – – – 250k – – – – – – – – – – 0 0.0% Max(1) 62.5kbps 125kbps 115.2kbps 230.4kbps 125kbps 250kbps Note: 1. UBRR = 0, Error = 0.
Table 25-6 Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) Baud Rate [bps] fosc = 8.0000MHz U2X = 0 U2X = 1 UBRR Error UBRR Error 2400 207 0.2% 416 4800 103 0.2% 9600 51 0.2% 14.4k 34 19.2k fosc = 11.0592MHz fosc = 14.7456MHz U2X = 0 U2X = 0 U2X = 1 Error UBRR Error UBRR Error UBRR Error -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.
Baud Rate [bps] fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz U2X = 0 U2X = 0 U2X = 0 U2X = 1 UBRR Error 115.2k 8 230.4k UBRR U2X = 1 U2X = 1 Error UBRR Error UBRR Error UBRR Error -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4% 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5M 1 0.0% 3 0.0% – – 4 -7.8% – – 4 0.0% 1M 0 0.0% 1 0.0% – – – – – – – Max.(1) 1Mbps 2Mbps 1.
25.11.1. UDRn – USART I/O Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
25.11.2. UCSRmA – USART Control and Status Register A Name: UCSRmA Offset: 0x9B Reset: 0x20 Property: – Bit 7 6 5 4 3 2 1 0 RXCm TXCm UDREm FEm DORm UPEm U2Xm MPCMm Access R R/W R R R R R/W R/W Reset 0 0 1 0 0 0 0 0 Bit 7 – RXCm: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (that is, does not contain any unread data).
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. Bit 0 – MPCMm: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode. When the MPCMm bit is written to one, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCMm setting.
25.11.3. UCSRmB – USART Control and Status Register B Name: UCSRmB Offset: 0x9A Reset: 0x00 Property: – Bit Access Reset 7 6 5 4 3 2 1 0 RXCIEm TXCIEm UDRIEm RXENm TXENm UCSZm2 RXB8m TXB8m R/W R/W R/W R/W R/W R/W R R/W 0 0 0 0 0 0 0 0 Bit 7 – RXCIEm: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC flag.
25.11.4. UCSRmC – USART Control and Status Register C Note: This register is not available in ATmega103 compatibility mode. Name: UCSRmC Offset: 0x20 Reset: 0x06 Property: When addressing I/O Registers as data space the offset address is 0x40 Bit 7 6 5 4 3 2 1 0 UMSELm UPMm1 UPMm0 USBSm UCSZm1 UCSZm0 UCPOLm R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 0 Access Reset Bit 6 – UMSELm: Mode Select This bit selects between Asynchronous and Synchronous mode of operation.
Bits 2:1 – UCSZmn: Character Size [n = 1:0] The UCSZm1:0 bits combined with the UCSZm2 bit in UCSRmB sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use. Table 25-11 UCSZ Bits Settings UCSZm2 UCSZm1 UCSZm0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit Bit 0 – UCPOLm: Clock Polarity This bit is used for synchronous mode only.
25.11.5. UBRRmL – USART Baud Rate Register Low Name: UBRRmL Offset: 0x99 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 UBBRm[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – UBBRm[7:0]: USARTm Baud Rate Register This is a 12-bit register which contains the USARTm baud rate. The UBRRmH contains the four most significant bits, and the UBRRmL contains the eight least significant bits of the USARTm baud rate.
25.11.6. UBBRmH – USART Baud Rate Register High Note: UBRRmH is not available in mega103 compatibility mode. Name: UBBRmH Offset: 0x20 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 UBRRm[3:0] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 3:0 – UBRRm[3:0]: USART Baud Rate Register The bits in this register ranges from UBRRm[11:8]. Refer to UBBRmL.
26. TWI - Two-wire Serial Interface 26.1. Features • • • • • • • • • • Overview The TWI module is comprised of several submodules, as shown in the following figure. All registers drawn in a thick line are accessible through the AVR data bus.
26.2.1. SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slewrate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section.
and wakes up the CPU, the TWI aborts operation and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the only enabled interrupt when entering Power-down. 26.2.5. Control Unit The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted.
Table 26-1 TWI Terminology 26.3.2. Term Description Master The device that initiates and terminates a transmission. The Master also generates the SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus. Electrical Interconnection As depicted in Figure 26-2 TWI Bus Interconnection on page 276, both bus lines are connected to the positive supply voltage through pull-up resistors.
seize control of the bus. A special case occurs when a new START condition is issued between a START and STOP condition. This is referred to as a REPEATED START condition, and is used when the Master wishes to initiate a new transfer without relinquishing control of the bus. After a REPEATED START, the bus is considered busy until the next STOP.
26.4.4. Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled.
26.5. Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • • An algorithm must be implemented allowing only one of the masters to complete the transmission.
Figure 26-9 Arbitration Between Two Masters START SD A from Master A Master A Loses Arbitration, SD AA SDA SD A from Master B SD A Line Synchroniz ed SCL Line Note that arbitration is not allowed between: • • • A REPEATED START condition and a data bit. A STOP condition and a data bit. A REPEATED START and a STOP condition. It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
Application Action Figure 26-10 Interfacing the Application to the TWI in a Typical Transmission 1. Application writes to TWCRto initiate transmission of START TWI Hardware Action TWI bus 1. 2. 3. 4. 5. 6. 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one, and TWSTA is written to zero. START 2.TWINT set. Status code indicates START condition sent SLA+W 5.
7. The application software should now examine the value of TWSR, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a STOP condition. Which value to write is described later on.
Assembly Code Example 26.6.1. Comments Wait for TWINT Flag set. This indicates wait3: in r16,TWCR sbrs r16,TWINT rjmp wait3 while (!(TWCR & (1<
26.6.2. Master Transmitter Mode In the Master Transmitter (MT) mode, a number of data bytes are transmitted to a Slave Receiver, see figure below. In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether MT or Master Receiver (MR) mode is to be entered: If SLA +W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus.
Figure 26-12 Formats and States in the Master Transmitter Mode MT Successfull transmission to a sla ve receiv er S SLA $08 W A DATA $18 A P $28 Next transfer star ted with a repeated star t condition RS SLA W $10 Not acknowledge received after the slave address A R P $20 MR Not acknowledge receiv ed after a data byte A P $30 Arbitration lost in sla ve address or data b yte A or A Other master contin ues A or A $38 Arbitration lost and addressed as sla ve A $68 From master to s
Figure 26-13 Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........ Device n R1 R2 SD A SCL A START condition is sent by writing to the TWI Control register (TWCR) a value of the type TWCR=1x10x10x: • TWCR.TWEN must be written to '1' to enable the 2-wire Serial Interface • TWCR.TWSTA must be written to '1' to transmit a START condition • TWCR.TWINT must be cleared by writing a '1' to it.
Table 26-4 Status codes for Master Receiver Mode Status Code (TWSR) Prescaler Bits are 0 Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWD Next Action Taken by TWI Hardware To TWCR STA STO TWIN T TWE A 0x08 A START condition has been transmitted Load SLA+R 0 0 1 X SLA+R will be transmitted ACK or NOT ACK will be received 0x10 A repeated START condition has been transmitted Load SLA+R or Load SLA+W 0 0 0 0 1 1 X X SLA+R will
Figure 26-14 Formats and States in the Master Receiver Mode MR Successfull reception from a sla v e receiv er S SLA $08 R A DATA $40 A DATA $50 A P $58 Next transf er star ted with a repeated star t condition RS SLA R $10 Not ac kno wledge received after the slave address A W P $48 Arbitration lost in sla ve address or data b yte MT A or A Other master contin ues A $38 Arbitration lost and addressed as sla ve A $68 From master to sla ve From slave to master 26.6.4.
Figure 26-15 Data transfer in Slave Receiver mode VCC Device 1 Device 2 SLAVE RECEIVER MASTER TRANSMITTER Device 3 ........ Device n R1 R2 SD A SCL To initiate the SR mode, the TWI (Slave) Address Register (TWAR) and the TWI Control Register (TWCR) must be initialized as follows: The upper seven bits of TWAR are the address to which the 2-wire Serial Interface will respond when addressed by a Master (TWAR.TWA[6:0]). If the LSB of TWAR is written to TWAR.
Table 26-5 Status Codes for Slave Receiver Mode Status Code (TWSR) Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWDR Prescaler Bits are 0 Next Action Taken by TWI Hardware To TWCR STA STO TWI NT TWE A 0x60 Own SLA+W has been received; ACK has been returned No TWDR action or No TWDR action X X 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 0x68 Arbitration l
Status Code (TWSR) Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWDR 0x98 To TWCR STA Prescaler Bits are 0 Next Action Taken by TWI Hardware STO TWI NT TWE A Previously addressed with general call; data has been Read data byte or 0 Read data byte or 0 0 0 1 1 0 1 Switched to the not addressed Slave mode; no recognition of own SLA or GCA received; NOT ACK has been Read data byte or 1 0 1 0 Switched to the not addressed Slave m
Figure 26-16 Formats and States in the Slave Receiver Mode Reception of the o wn sla ve address and one or more data b ytes.
Figure 26-17 Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 SLAVE TRANSMITTER MASTER RECEIVER Device 3 ........ Device n R1 R2 SD A SCL To initiate the SR mode, the TWI (Slave) Address Register (TWAR) and the TWI Control Register (TWCR) must be initialized as follows: The upper seven bits of TWAR are the address to which the 2-wire Serial Interface will respond when addressed by a Master (TWAR.TWA[6:0]). If the LSB of TWAR is written to TWAR.
Table 26-6 Status Codes for Slave Transmitter Mode Status Code (TWSR) Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWDR Prescaler Bits are 0 Next Action Taken by TWI Hardware To TWCR STA STO TWI NT TWE A 0xA8 Own SLA+R has been received; ACK has been returned Load data byte or Load data byte X X 0 0 1 1 0 1 Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received 0
Figure 26-18 Formats and States in the Slave Transmitter Mode Reception of the o wn sla ve address and one or more data b ytes S SLA R A DATA A $A8 Arbitration lost as master and addressed as sla ve DATA $B8 A P or S $C0 A $B0 Last data b yte tr ansmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S $C8 DATA From master to sla ve From slave to master 26.6.6.
1. 2. 3. 4. The transfer must be initiated. The EEPROM must be instructed what location should be read. The reading must be performed. The transfer must be finished. Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed.
• • Two or more masters are accessing the same Slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a '1' on SDA while another Master outputs a zero will lose the arbitration. Losing masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. Two or more masters are accessing different slaves.
26.8.1. TWBR – TWI Bit Rate Register Name: TWBR Offset: 0x70 Reset: 0x00 Property: – Bit Access Reset 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TWBRn: TWI Bit Rate Register [n = 7:0] TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
26.8.2. TWCR – TWI Control Register The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.
STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state. Bit 3 – TWWC: TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high. Bit 2 – TWEN: TWI Enable The TWEN bit enables TWI operation and activates the TWI interface.
26.8.3. TWSR – TWI Status Register Name: TWSR Offset: 0x71 Reset: 0xF8 Property: – Bit 7 6 5 4 3 1 0 TWS7 TWS6 TWS5 TWS4 TWS3 2 TWPS1 TWPS0 Access R R R R R R/W R/W Reset 1 1 1 1 1 0 0 Bit 7 – TWS7: TWI Status Bit 7 The TWS[7:3] reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes are described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value.
26.8.4. TWDR – TWI Data Register In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set.
26.8.5. TWAR – TWI (Slave) Address Register The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as Slaves by other Masters. The LSB of TWAR is used to enable recognition of the general call address (0x00).
27. Analog Comparator 27.1. Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
Table 27-1 Analog Comparator Multiplexed Input 27.3.
27.3.1. SFIOR – Analog Comparator Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
27.3.2. ACSR – Analog Comparator Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
Bits 1:0 – ACISn: Analog Comparator Interrupt Mode Select [n = 1:0] These bits determine which comparator events that trigger the Analog Comparator interrupt. Table 27-2 ACIS[1:0] Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge.
28. ADC - Analog to Digital Converter 28.1. Features • • • • • • • • • • • • • • • • 28.2. 10-bit Resolution 0.75 LSB Integral Non-Linearity ±1.5 LSB Absolute Accuracy 13 - 260μs Conversion Time Up to 15ksps at Maximum Resolution 8 Multiplexed Single Ended Input Channels 7 Differential Input Channels 2 Differential Input Channels with Optional Gain of 10x and 200x Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 2.7 - VCC Differential ADC Voltage Range Selectable 2.
Figure 28-1 Analog to Digital Converter Block Schematic Operation ADC CONVERSION COMPLETE IRQ 15 0 ADC DATA REGISTER (ADCH/ADCL) ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADFR ADEN ADSC MUX1 ADC CTRL. & ST ATUS REGISTER (ADCSRA) MUX0 MUX2 MUX4 MUX3 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS MUX DECODER CHANNEL SELECTION PRESCALER AVCC CONVERSION LOGIC INTERNAL 2.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. Prescaling and Conversion Timing Figure 28-3 ADC Prescaler ADEN START Reset CK/64 CK/128 CK/32 CK/8 CK/16 CK/4 7-BIT ADC PRESCALER CK CK/2 28.4.
Figure 28-4 ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion Cycle Number 1 12 2 13 14 16 15 17 18 19 20 21 23 22 24 25 1 2 3 ADC Clock ADEN ADSC ADIF Sign and MSB of Result ADCH LSB of Result ADCL MUX and REFS Update Conversion Complete Sample and Hold MUX and REFS Update Figure 28-5 ADC Timing Diagram, Single Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 Next Conversion 8 9 10 11 12 13 1 2 3 ADC Clock ADSC
Figure 28-7 ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Conversion Complete Sample and Hold MUX and REFS Update Table 28-1 ADC Conversion Time 28.4.1. Condition Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 Auto Triggered conversions 2 13.
the extended conversions will be valid. Refer to Prescaling and Conversion Timing on page 314 for timing details. 28.5. Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started.
When switching to a differential gain channel, the first conversion result may have a poor accuracy due to the required settling time for the automatic offset cancellation circuitry. The user should preferably disregard the first conversion result. 28.5.2. ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.
The ADC is optimized for analog signals with an output impedance of approximately 10kΩ or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedance sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor.
Figure 28-9 ADC Power Connections (AD0) PA0 VCC GND 10µH 52 53 (ADC7) P F7 54 (ADC6) P F6 55 (ADC5) P F5 56 (ADC4) P F4 57 (ADC3) P F3 58 (ADC2) P F2 59 (ADC1) P F1 60 (ADC0) P F0 61 AREF 62 GND 63 AVCC 64 1 P EN 100nF 51 28.6.3. Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible.
Figure 28-10 Offset Error Output Code Ideal ADC Actual ADC Offset Error • VREF Input Voltage Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB.
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 28-13 Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 • • 28.7. VREF Input Voltage Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
Figure 28-14 Differential Measurement Range Output Code 0x1FF 0x000 - VREF /GAIN 0 0x3FF VREF /GAIN Diffe re ntia l Input Volta ge (Volts ) 0x200 Table 28-2 Correlation Between Input Voltage and Output Codes VADCn Read Code Corresponding decimal value VADCm + VREF /GAIN 0x1FF 511 VADCm + 511/512 VREF /GAIN 0x1FF 511 VADCm + 511/512 VREF /GAIN 0x1FE 510 :. :. :. VADCm + 1/512 VREF /GAIN 0x001 1 VADCm 0x000 0 VADCm - 1/512 VREF /GAIN 0x3FF -1 :. :. :.
Voltage on ADC3 is 300mV, voltage on ADC2 is 500mV. ADCR = 512 × 10 × (300 - 500) / 2560 = -400 = 0x270 ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. 28.8.
28.8.1. ADMUX – ADC Multiplexer Selection Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
Table 28-4 Input Channel and Gain Selections MUX[4:0] Single Ended Input 00000 ADC0 00001 ADC1 00010 ADC2 00011 ADC3 00100 ADC4 00101 ADC5 00110 ADC6 00111 ADC7 Positive Differential Input Negative Differential Input Gain N/A 01000(1) Reserved ADC0 ADC0 10x 01001 Reserved ADC1 ADC0 10x 01010(1) ADC0 ADC0 200x 01011 ADC1 ADC0 200x 01100 ADC2 ADC2 10x 01101 ADC3 ADC2 10x 01110 ADC2 ADC2 200x 01111 ADC3 ADC2 200x 10000 ADC0 ADC1 1x 10001 ADC1 ADC1
MUX[4:0] Single Ended Input 11110 1.22V (VBG) 11111 0V (GND) Positive Differential Input Negative Differential Input Gain N/A Note: 1. Can be used for offset calibration.
28.8.2. ADCSRA – ADC Control and Status Register A When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
Table 28-5 ADC Prescaler Selections ADPS[2:0] Division Factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Atmel ATmega64A [DATASHEET] Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015 329
28.8.3. ADCL – ADC Data Register Low (ADLAR=0) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
28.8.4. ADCH – ADC Data Register High (ADLAR=0) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
28.8.5. ADCL – ADC Data Register Low (ADLAR=1) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
28.8.6. ADCH – ADC Data Register High (ADLAR=1) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
28.8.7. ADCSRB – ADC Control and Status Register B Name: ADCSRB Offset: 0x8E Reset: 0x00 Property: – Bit 7 6 5 4 3 Access Reset 2 1 0 ADTS2 ADTS1 ADTS0 R/W R/W R/W 0 0 0 Bits 2:0 – ADTSn: ADC Auto Trigger Source [n = 2:0] If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected interrupt flag.
29. JTAG Interface and On-chip Debug System 29.1. Features • • • • • • 29.2. JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the IEEE std. 1149.
TAP – Test Access Port The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are: • • • • TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine. TCK: Test clock. JTAG operation is synchronous to TCK. TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). TDO: Test Data Out.
Figure 29-2 TAP Controller State Diagram 1 Te s t-Logic-Re s e t 0 0 Run-Te s t/Idle 1 S e le ct-DR S ca n 1 S e le ct-IR S ca n 0 0 1 1 Ca pture -DR Ca pture -IR 0 0 S hift-DR S hift-IR 0 1 Exit1-DR 0 P a us e -DR 0 0 P a us e -IR 1 1 0 Exit2-DR Exit2-IR 1 1 Upda te -DR 29.4.
• • • the JTAG instruction register from the TDI input at the rising edge of TCK. The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR state. The MSB of the instruction is shifted in when this state is left by setting TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the TDO pin.
• • • • 3 Single Program Memory break points + 1 single Data Memory break point 2 Single Program Memory break points + 2 single Data Memory break points 2 Single Program Memory break points + 1 Program Memory break point with mask (“range break point”) 2 Single Program Memory break points + 1 Data Memory break point with mask (“range break point”) A debugger, like the Atmel Studio®, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user.
29.8. Using the JTAG Programming Capabilities Programming of AVR parts via JTAG is performed via the four-pin JTAG port, TCK, TMS, TDI, and TDO. These are the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN fuse must be programmed and the JTD bit in the MCUCSR Register must be cleared to enable the JTAG Test Access Port.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of the data register path will show the ID-code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have the AVR device in reset during test mode.
29.11.2.2. Part Number The part number is a 16-bit code identifying the component. The JTAG Part Number for ATmega64A is listed in the table below. Table 29-1 AVR JTAG Part Number Part Number JTAG Part Number (Hex) ATmega64A 0x9602 29.11.2.3. Manufacturer ID The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is listed in the table below. Table 29-2 Manufacturer ID Manufacturer JTAG Manufacturer ID (Hex) ATMEL 0x01F 29.11.3.
29.12. Boundry-scan Specific JTAG Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not implemented, but all outputs with tri-state capability can be set in high-impedant state by using the AVR_RESET instruction, since the initial state for all port pins is tri-state.
• Shift-DR: The Reset Register is shifted by the TCK input. 29.12.5. BYPASS; 0xF Mandatory JTAG instruction selecting the Bypass Register for Data Register. The active states are: • • Capture-DR: Loads a logic “0” into the Bypass Register. Shift-DR: The Bypass Register cell between TDI and TDO is shifted. 29.13.
Figure 29-5 Boundary-scan Cell for Bi-directional Port Pin with Pull-Up Function.
Figure 29-6 General Port Pin Schematic diagram S e e Bounda ry-S ca n de s cription for de ta ils ! P UExn P UD D Q DDxn Q CLR RES ET OCxn WDx D Q P xn ODxn PORTxn Q IDxn CLR RES ET WP x DATA BUS RDx RRx S LEEP S YNCHRONIZER D Q D RP x Q PINxn L Q Q CLK I/O P UD: P UExn: OCxn: ODxn: IDxn: S LEEP : P ULLUP DIS ABLE P ULLUP ENABLE for pin P xn OUTP UT CONTROL for pin P xn OUTP UT DATA to pin P xn INP UT DATA from pin P xn S LEEP CONTROL WDx: RDx: WP x: RRx: RP x: CLK I/O :
Figure 29-7 Additional Scan Signal for the Two-wire Interface PUExn OCxn ODxn Pxn TWIEN SRC Slew-rate limited IDxn 29.13.3. Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard Reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in the figure below is inserted both for the 5V Reset signal; RSTT, and the 12V Reset signal; RSTHV.
The figure below shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general boundary-scan cell, while the Oscillator/Clock output is attached to an observe-only cell. In addition to the main clock, the Timer Oscillator is scanned in the same way. The output from the internal RC Oscillator is not scanned, as this Oscillator does not have external connections.
chain, so the boundary scan chain can not make a XTAL Oscillator requiring internal capacitors to run unless the fuse is correctly programmed. 29.13.5. Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in the first figure below. The Boundary-scan cell from the second figure below is attached to each of these signals. The signals are described in Table 29-4 Boundary-scan Signals for the Analog Comparator on page 350.
Table 29-4 Boundary-scan Signals for the Analog Comparator Signal Name Direction as Seen from the Comparator Description Recommended Input Output values when when not in Use Recommended Inputs are Used AC_IDLE Input Turns off Analog comparator when true 1 Depends upon μC code being executed ACO Output Analog Comparator Output Will become input to μC code being executed 0 ACME Input Uses output signal from ADC mux when true 0 Depends upon μC code being executed ACBG Input Bandgap Refere
Table 29-5 Boundary-scan Signals for the ADC Signal Name Direction as Description Seen from the ADC Recommend ed Input when not in Use Output Values when Recommend ed Inputs are Used, and CPU is not Using the ADC COMP Output Comparator Output 0 0 ACLK Input Clock signal to gain stages implemented as 0 Switch-cap filters 0 ACTEN Input Enable path from gain stages to the comparator 0 0 ADCBGEN Input Enable Band-gap reference as negative input to comparator 0 0 ADCEN Input Power-on sig
Signal Name Direction as Description Seen from the ADC Recommend ed Input when not in Use Output Values when Recommend ed Inputs are Used, and CPU is not Using the ADC IREFEN Input Enables Band-gap reference as AREF signal to DAC 0 0 MUXEN_7 Input Input Mux bit 7 0 0 MUXEN_6 Input Input Mux bit 6 0 0 MUXEN_5 Input Input Mux bit 5 0 0 MUXEN_4 Input Input Mux bit 4 0 0 MUXEN_3 Input Input Mux bit 3 0 0 MUXEN_2 Input Input Mux bit 2 0 0 MUXEN_1 Input Input Mux bit 1 0
gain stages require fast operation and accurate timing which is difficult to obtain when used in a scan chain. Details concerning operations of the differential gain stage is therefore not provided. The AVR ADC is based on the analog circuitry shown in Figure 29-12 Analog to Digital Converter on page 350 with a successive approximation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is usually to ensure that an applied analog voltage is measured within some limits.
Step Actions ADCEN DAC MUXEN HOLD PRECH PA3. Data PA3. Control PA3. Pullup_ Enable 7 1 0x200 0x08 0 1 0 0 0 8 1 0x200 0x08 1 1 0 0 0 9 1 0x143 0x08 1 1 0 0 0 10 1 0x143 0x08 1 0 0 0 0 11 Verify the 1 COMP bit scanned out to be 1 0x200 0x08 1 1 0 0 0 Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency.
Bit Number Signal Name Module 200 COMP ADC 199 PRIVATE_SIGNAL1(1) 198 ACLK 197 ACTEN 196 PRIVATE_SIGNAL1(2) 195 ADCBGEN 194 ADCEN 193 AMPEN 192 DAC_9 191 DAC_8 190 DAC_7 189 DAC_6 188 DAC_5 187 DAC_4 186 DAC_3 185 DAC_2 184 DAC_1 183 DAC_0 182 EXTCH 181 G10 180 G20 179 GNDEN 178 HOLD 177 IREFEN 176 MUXEN_7 Atmel ATmega64A [DATASHEET] Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015 355
Bit Number Signal Name Module 175 MUXEN_6 ADC 174 MUXEN_5 173 MUXEN_4 172 MUXEN_3 171 MUXEN_2 170 MUXEN_1 169 MUXEN_0 168 NEGSEL_2 167 NEGSEL_1 166 NEGSEL_0 165 PASSEN 164 PRECH 163 SCTEST 162 ST 161 VCCREN 160 PEN Programming enable (observe only) Atmel ATmega64A [DATASHEET] Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015 356
Bit Number Signal Name Module 159 PE0.Data Port E 158 PE0.Control 157 PE0.Pullup_Enable 156 PE1.Data 155 PE1.Control 154 PE1.Pullup_Enable 153 PE2.Data 152 PE2.Control 151 PE2.Pullup_Enable 150 PE3.Data 149 PE3.Control 148 PE3.Pullup_Enable 147 PE4.Data 146 PE4.Control 145 PE4.Pullup_Enable 144 PE5.Data 143 PE5.Control 142 PE5.Pullup_Enable 141 PE6.Data 140 PE6.Control 139 PE6.Pullup_Enable 138 PE7.Data 137 PE7.Control 136 PE7.
Bit Number Signal Name Module 135 PB0.Data Port B 134 PB0.Control 133 PB0.Pullup_Enable 132 PB1.Data 131 PB1.Control 130 PB1.Pullup_Enable 129 PB2.Data 128 PB2.Control 127 PB2.Pullup_Enable 126 PB3.Data 125 PB3.Control 124 PB3.Pullup_Enable 123 PB4.Data 122 PB4.Control 121 PB4.Pullup_Enable 120 PB5.Data 119 PB5.Control 118 PB5.Pullup_Enable 117 PB6.Data 116 PB6.Control 115 PB6.Pullup_Enable 114 PB7.Data 113 PB7.Control 112 PB7.Pullup_Enable 111 PG3.
Bit Number Signal Name Module 103 RSTT 102 RSTHV Reset Logic (Observe-only) 101 EXTCLKEN 100 OSCON 99 RCOSCEN 98 OSC32EN 97 EXTCLK (XTAL1) 96 OSCCK 95 RCCK 94 OSC32CK 93 TWIEN Enable signals for main Clock/Oscillators Clock input and Oscillators for the main clock (Observe-only) TWI Atmel ATmega64A [DATASHEET] Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015 359
Bit Number Signal Name Module 92 PD0.Data Port D 91 PD0.Control 90 PD0.Pullup_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pullup_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pullup_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pullup_Enable 80 PD4.Data 79 PD4.Control 78 PD4.Pullup_Enable 77 PD5.Data 76 PD5.Control 75 PD5.Pullup_Enable 74 PD6.Data 73 PD6.Control 72 PD6.Pullup_Enable 71 PD7.Data 70 PD7.Control 69 PD7.Pullup_Enable 68 PG0.Data Port G 67 PG0.
Bit Number Signal Name Module 62 PC0.Data Port C 61 PC0.Control 60 PC0.Pullup_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pullup_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pullup_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pullup_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pullup_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pullup_Enable 44 PC6.Data 43 PC6.Control 42 PC6.Pullup_Enable 41 PC7.Data 40 PC7.Control 39 PC7.Pullup_Enable 38 PG2.Data 37 PG2.Control 36 PG2.
Bit Number Signal Name Module 31 PA6.Control Port A 30 PA6.Pullup_Enable 29 PA5.Data 28 PA5.Control 27 PA5.Pullup_Enable 26 PA4.Data 25 PA4.Control 24 PA4.Pullup_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pullup_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pullup_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pullup_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pullup_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pullup_Enable 8 PF2.Data 7 PF2.Control 6 PF2.
Note: 1. PRIVATE_SIGNAL1 should always scanned in as zero. 2. PRIVATE_SIGNAL2 should always scanned in as zero. 29.15. Boundary-scan Description Language Files Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description. 29.16.
29.16.1. OCDR – On-chip Debug Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
29.16.2. MCUCSR – MCU Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions.
30. BTLDR - Boot Loader Support – Read-While-Write Self-Programming 30.1. Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 1.
30.4. Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-Write (NRWW) section.
Figure 30-1 Read-While-Write vs.
Figure 30-2 Memory Sections Program Memory BOOTSZ = '10' Program Memory BOOTSZ = '11' 0x0000 Application Flash Section Read-While-Write Section End Application Start Boot Loader Flashend 0x0000 Application Flash Section No Read-While-Write Section End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Application Flash Section End RWW Start NRWW Application Flash Section Boot Loader Flash Section End Application Start Boot Loader Flashe
See tables below for further details. The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 3) does not control reading nor writing by LPM/SPM, if it is attempted.
once the Boot Reset Fuse is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 30-4 Boot Reset Fuse(1) BOOTRST Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset, as described in the Boot Loader Parameters Note: 1. '1' means unprogrammed, '0' means programmed. 30.7.
Figure 30-3 Addressing the Flash During SPM(1) BIT 15 ZPAGEMSB ZPCMSB 1 0 0 Z - REGISTER PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 1. The different variables used in the figure are listed in Table 30-7 Read-While-Write Limit, ATmega64A(1) on page 379. 2.
If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased.
Loader, and further software updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software changes. 30.8.6. Prevent Reading the RWW Section During Self-Programming During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for reading.
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock Bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low bits (FLB) will be loaded in the destination register as shown below.
Table 30-5 SPM Programming Time(1) Symbol Min. Programming Time Max. Programming Time Flash write (Page Erase, Page Write, and write Lock bits 3.7ms by SPM) 4.5ms Note: 1. Minimum and maximum programming time is per individual operation. 30.8.12.
call Do_spm ; transfer data from RAM to Flash page buffer ldi looplo, low(PAGESIZEB) ;init loop variable ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 Wrloop: ld r0, Y+ ld r1, Y+ ldi spmcsrval, (1<
lpm r0, Z+ ld r1, Y+ cpse r0, r1 jmp Error sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256 brne Rdloop ; return to RWW section ; verify that RWW section is safe to read Return: lds temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcsrval, (1<
sbic EECR, EEWE rjmp Wait_ee ; SPM timed sequence sts SPMCSR, spmcsrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret 30.8.13. ATmega64A Boot Loader Parameters In the following tables, the parameters used in the description of the self programming are given.
Table 30-8 Explanation of Different Variables Used in Figure and the Mapping to the Z-pointer, ATmega64A(3) Variable Corresponding Zvalue(1) Description(2) PCMSB 14 Most significant bit in the program counter. (The program counter is 15 bits PC[14:0]) PAGEMSB 6 Most significant bit which is used to address the words within one page (128 words in a page requires 7 bits PC [6:0]). ZPCMSB Z15(1) Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1.
30.9.1. SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored.
31. 31.1. Memory Programming Program and Data Memory Lock Bits The ATmega64A provides six Lock bits. These can be left unprogrammed ('1') or can be programmed ('0') to obtain the additional features listed in table Lock Bit Protection Modes below. The Lock Bits can only be erased to “1” with the Chip Erase command. Table 31-1 Lock Bit Byte Bit No.
Memory Lock Bits Protection Type LB Mode LB2 LB1 4 0 1 BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 3 0 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
2. See WDTCR - Watchdog Timer Control Register for details. Table 31-4 Fuse High Byte Fuse High Byte Bit No. Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(5) 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
Fuse Low Byte Bit No. Description Default Value CKSEL1 1 Select Clock source 0 (programmed)(2) CKSEL0 0 Select Clock source 1 (unprogrammed)(2) Note: 1. The default value of SUT1:0 results in maximum start-up time. See table Start-up Times for the Internal Calibrated RC Oscillator Clock Selection in section Calibrated Internal RC Oscillator for details. 2. The default setting of CKSEL3:0 results in Internal RC Oscillator @ 1MHz.
31.5. Page Size Table 31-7 Number of Words in a Page and number of Pages in the Flash Flash Size Page Size PCWORD Number of Pages PCPAGE PCMSB 32K words (64K bytes) 128 words PC[6:0] 256 PC[14:7] 14 Table 31-8 Number of Words in a Page and number of Pages in the EEPROM EEPROM Size Page Size PCWORD Number of Pages PCPAGE EEAMSB 2K bytes 8 bytes EEA[2:0] 256 EEA[8:2] 10 31.6. Parallel Programming 31.6.1.
31.6.3. Chip Erase The Chip Erase will erase the Flash and EEPROM memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. Note: The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. Load Command “Chip Erase”: 1. 2. 3. 4. 5. 6. 31.6.4. Set XA1, XA0 to “10”. This enables command loading. Set BS1 to “0”.
Step F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded. While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in the following figure, Addressing the Flash Which is Organized in Pages, in this section.
Note: PCPAGE and PCWORD are listed in the section Page Size. Figure 31-2 Programming the Flash Waveform F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: “XX” is don’t care. The letters refer to the programming description above. 31.6.5. Programming the EEPROM The EEPROM is organized in pages.
Figure 31-3 Programming the EEPROM Waveforms K DATA A G B 0x11 ADDR. HIGH ADDR. LOW C DATA E XX B ADDR. LOW C E DATA L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 31.6.6. Reading the Flash The algorithm for reading the Flash memory is as follows (Please refer to Programming the Flash on page 388 in this chapter for details on Command and Address loading): 1. 2. 3. 4. 5. 6. 31.6.7.
1. 2. 3. 4. 5. Step A: Load Command “0100 0000”. Step C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. Set BS1 to “1” and BS2 to “0”. This selects high data byte. Give WR a negative pulse and wait for RDY/BSY to go high. Set BS1 to “0”. This selects low data byte. 31.6.10. Programming the Extended Fuse Bits The algorithm for programming the Extended Fuse bits is as follows (Please refer to Programming the Flash for details on Command and Data loading): 1. 2. 3. 4. 5.
2. 3. 4. 5. 6. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now be read at DATA (“0” means programmed). Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at DATA (“0” means programmed).
31.7. Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the device. Pulses are assumed to be at least 250ns unless otherwise noted. 31.7.1. Signal Names In this section, some pins of this device are referenced by signal names describing their functionality during parallel programming, refer to the following figure and table Pin Name Mapping in this section.
Signal Name in Programming Mode Pin Name I/O Function XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 PAGEL PD7 I Program memory and EEPROM Data Page Load BS2 PA0 I Byte Select 2 (“0” selects Low byte, “1” selects second High byte) DATA PB7-0 I/O Bi-directional Data bus (Output when OE is low) Table 31-10 Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 31-11 XA1
31.8. Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. Note: The pin mapping for SPI programming is listed in the following section. Not all parts use the SPI pins dedicated for the internal SPI interface.
1. 2. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. VCC - 0.3 < AVCC < VCC + 0.3V, however, AVCC should always be within 2.7 - 5.5V. When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.
6. 7. 8. before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 31-14 Minimum Wait Delay Before Writing the Next Flash or EEPROM Location, VCC = 5V ± 10% on page 398). In a chip erased device, no 0xFFs in the data file(s) need to be programmed. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.
Figure 31-8 Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 31-15 Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable SPI Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation Read Fuse Bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse Bits. “0” = programmed, “1” = unprogrammed. See table Fuse Low Byte for details. Read Extended Fuse bits 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = programmed, “1” = unprogrammed. See table Fuse Low Byte for details. Read Fuse High Bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which data register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in the figure below.
Register is selected as Data Register. Note that the reset will be active as long as there is a logic 'one' in the Reset Chain. The output from this chain is not latched. The active states are: • Shift-DR: The Reset Register is shifted by the TCK input. 31.10.3. PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-bit Programming Enable Register is selected as data register.
31.10.7. Data Registers The data registers are selected by the JTAG instruction registers described in section Programming Specific JTAG Instructions on page 400. The data registers relevant for programming operations are: • • • • • Reset Register Programming Enable Register Programming Command Register Virtual Flash Page Load Register Virtual Flash Page Read Register 31.10.8. Reset Register The Reset Register is a Test Data Register used to reset the part during programming.
Programming Instruction Set is shown in the following table. The state sequence when shifting in the programming commands is illustrated in State Machine Sequence for Changing/Reading the Data Word further down in this section.
Instruction TDI sequence TDO sequence Notes 2f. Latch Data 0110111_00000000 1110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 0110101_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 2h. Poll for Page Write complete 0110111_00000000 xxxxxox_xxxxxxxx 3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 3c.
Instruction TDI sequence TDO sequence Notes 6c. Write Fuse Extended byte 0111011_00000000 0111001_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 0111011_00000000 xxxxxxx_xxxxxxxx 0111011_00000000 xxxxxxx_xxxxxxxx 6d. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 6e. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6f.
Instruction TDI sequence TDO sequence Notes 8f. Read Fuses and Lock bits 0111010_00000000 0111110_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo (5) fuse ext. byte 0110010_00000000 xxxxxxx_oooooooo fuse high byte 0110110_00000000 xxxxxxx_oooooooo fuse low byte 0110111_00000000 xxxxxxx_oooooooo lock bits 9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 9c.
Figure 31-12 State Machine Sequence for Changing/Reading the Data Word 1 Te s t-Logic-Re s e t 0 0 Run-Te s t/Idle 1 S e le ct-DR S ca n 1 S e le ct-IR S ca n 0 0 1 1 Ca pture -DR Ca pture -IR 0 0 S hift-DR S hift-IR 0 1 Exit1-DR 1 Exit1-IR 0 0 Pa us e -DR 0 0 Pa us e -IR 1 1 0 Exit2-DR Exit2-IR 1 1 Upda te -DR 1 0 1 1 0 1 Upda te -IR 0 1 0 Related Links Page Size on page 387 31.10.11.
Figure 31-13 Virtual Flash Page Load Register S TROBES TDI S ta te ma chine ADDRES S Fla s h EEP ROM Fus e s Lock Bits D A T A TDO 31.10.12. Virtual Flash Page Read Register The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte by byte.
Figure 31-14 Virtual Flash Page Read Register S TROBES TDI S ta te ma chine ADDRES S Fla s h EEP ROM Fus e s Lock Bits D A T A TDO 31.10.13. Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 31-16 JTAG Programming Instruction Set on page 404. 31.10.14. Entering Programming Mode 1. 2. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. 31.10.15.
31.10.17. Programming the Flash Before programming the Flash a Chip Erase must be performed. See Performing Chip Erase on page 410. 1. 2. 3. 4. 5. Enter JTAG instruction PROG_COMMANDS. Enable Flash write using programming instruction 2a. Load address high byte using programming instruction 2b. Load address low byte using programming instruction 2c. Load data using programming instructions 2d, 2e and 2f. 6. 7. 8. Repeat steps 4 and 5 for all instruction words in the page.
3. 4. 5. 6. 7. Load the page address using programming instructions 3b and 3c. PCWORD (refer to table Command Byte Bit Coding in section Parallel Programming Parameters, Pin Mapping, and Commands) is used to address within one page and must be written as 0. Enter JTAG instruction PROG_PAGEREAD. Read the entire page by shifting out all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page.
5. 6. 7. 8. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to table Parallel Programming Characteristics, VCC = 5V ±10% in chapter Parallel Programming Characteristics). Load data byte using programming instructions 6e. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse. Write Fuse high byte using programming instruction 6f.
5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. 31.10.25. Reading the Calibration Byte 1. 2. 3. 4. Enter JTAG instruction PROG_COMMANDS. Enable Calibration byte read using programming instruction 10a. Load address 0x00 using programming instruction 10b. Read the calibration byte using programming instruction 10c.
32. Electrical Characteristics – TA = -40°C to 85°C Table 32-1 Absolute Maximum Ratings* 32.1. Operating Temperature -55°C to +125°C Storage Temperature -65°C to +150°C Voltage on any Pin except RESET with respect to Ground -0.5V to VCC+0.5V Voltage on RESET with respect to Ground -0.5V to +13.0V Maximum Operating Voltage 6.0V DC Current per I/O Pin 40.0mA DC Current VCC and GND Pins 200.0 - 400.
Symbol Parameter Condition IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1.0 IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) 1.0 RRST Reset Pull-up Resistor 30 60 RPEN PEN Pull-up Resistor 30 60 RPU I/O Pin Pull-up Resistor 20 50 Power Supply Current ICC Power-down mode(5) Min Typ Max Active 4MHz, VCC = 3V 2.5 5 Active 8MHz, VCC = 5V 8.1 20 Idle 4MHz, VCC = 3V 0.7 2 Idle 8MHz, VCC = 5V 2.
5. 5. The sum of all IOH, for ports F0 - F7, should not exceed 100mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. Minimum VCC for Power-down is 2.5V. Related Links External Clock on page 57 32.2. Speed Grades Figure 32-1 Maximum Frequency vs. Vcc 16 MHz 8 MHz S a fe Ope ra ting Are a 2.7V 32.3. 4.5V 5.5V Clock Characteristics Related Links External Clock on page 57 32.3.1.
32.3.2. External Clock Drive Table 32-3 External Clock Drive(1) Symbol Parameter VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Units Min Max Min Max 8 0 16 1/tCLCL Oscillator Frequency 0 MHz tCLCL Clock Period 125 62.5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1.6 0.5 μs tCHCL Fall Time 1.6 0.5 μs ΔtCLCL Change in period from one clock cycle to the next 2 2 % Note: 1. Refer to External Clock for details.
Symbol Parameter Condition Min Typ Max Units 1.15 1.23 1.35 V μs VBG Bandgap reference voltage tBG Bandgap reference start-up time 40 IBG Bandgap reference current consumption 10 70 μA Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). 2. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test.
Symbol Parameter Condition Min Max Units tHD;STA fSCL ≤ 100kHz 4.0 – μs fSCL > 100kHz 0.6 – μs fSCL ≤ 100kHz 4.7 – μs fSCL > 100kHz 1.3 – μs fSCL ≤ 100kHz 4.0 – μs fSCL > 100kHz 0.6 – μs fSCL ≤ 100kHz 4.7 – μs fSCL > 100kHz 0.6 – μs fSCL ≤ 100kHz 0 3.45 μs fSCL > 100kHz 0 0.9 μs fSCL ≤ 100kHz 250 – ns fSCL > 100kHz 100 – ns fSCL ≤ 100kHz 4.0 – μs fSCL > 100kHz 0.6 – μs fSCL ≤ 100kHz 4.
32.6.
Note: 1. The timing requirements shown in the first figure in this section (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 32-7 Parallel Programming Characteristics, VCC = 5V ± 10% Symbol Parameter Min Typ Max Units VPP Programming Enable Voltage 11.5 12.
Table 32-8 SPI Timing Parameters Description Mode Min 1 SCK period Master See Table 24-5 Relationship between SCK and Oscillator Frequency on page 242 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
SPI interface timing requirements (Slave Mode) 18 SS 10 9 16 S CK (CP OL = 0) 11 11 S CK (CP OL = 1) 13 MOS I (Da ta Input) 14 12 MS B ... LS B 17 15 MIS O (Da ta Output) 32.8. MS B ... LS B X ADC Characteristics Table 32-9 ADC Characteristics, Single Ended Channels, -40°C – 85°C Symbol Parameter Resolution Condition Min Single Ended Conversion 10 Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 1.
Symbol Parameter Condition Offset Error Min Single Ended Conversion VREF = 4V, VCC = 4V Typ Max Units 0.75 LSB ADC clock = 200kHz Clock Frequency Conversion Time Free Running Conversion 50 1000 kHz 13 260 μs AVCC Analog Supply Voltage VCC 0.3(1) VCC + 0.3(2) V VREF Reference Voltage 2.0 AVCC V VIN Input voltage GND VREF V Input bandwidth VINT Internal Voltage Reference 2.4 RREF Reference Input Resistance RAIN Analog Input Resistance 38.5 kHz 2.56 2.
Symbol Parameter Gain Error Min(1) Typ(1) Max(1) Units Gain = 1x 1.6 % Gain = 10x 1.6 % Gain = 200x 0.3 % Gain = 1x 1.5 LSB 1 LSB 6 LSB Condition VREF = 4V, VCC = 5V ADC clock = 50 200kHz Gain = 10x Offset Error VREF = 4V, VCC = 5V ADC clock = 50 200kHz Gain = 200x VREF = 4V, VCC = 5V ADC clock = 50 200kHz Clock Frequency 50 200 kHz Conversion Time 13 260 μs AVCC Analog Supply Voltage VCC 0.3(1) VCC + 0.3(2) V VREF Reference Voltage 2.0 AVCC - 0.
32.9. External Data Memory Timing Table 32-11 External Data Memory Characteristics, 4.5V - 5.5V, No Wait-state Symbol Parameter 8MHz Oscillator Variable Oscillator Min Min Max 0.0 16 Max Unit 0 1/tCLCL Oscillator Frequency MHz 1 tLHLL ALE Pulse Width 115 1.0tCLCL-10 ns 2 tAVLL Address Valid A to ALE Low 57.5 0.
Symbol Parameter 8MHz Oscillator Variable Oscillator Min Min Max Unit Max 15 tDVWH Data Valid to WR High 240 2.0tCLCL ns 16 tWLWH WR Pulse Width 240 2.0tCLCL-10 ns Table 32-13 External Data Memory Characteristics, 4.5V - 5.5V, SRWn1 = 1, SRWn0 = 0 Symbol 0 1/tCLCL Parameter 4MHz Oscillator Variable Oscillator Min Min Max 0.0 16 MHz 3.0tCLCL-50 ns Max Oscillator Frequency 325 Unit 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 365 3.
Symbol Parameter 4MHz Oscillator Variable Oscillator Min Min Max Unit Max 6 tAVWL Address Valid to WR Low 235 1.0tCLCL-15 ns 7 tLLWL ALE Low to WR Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) ns 8 tLLRL ALE Low to RD Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) ns 9 tDVRH Data Setup to RD High 45 10 tRLDV Read Low to Data Valid 11 tRHDX Data Hold After RD High 0 0 ns 12 tRLRH RD Pulse Width 235 1.0tCLCL-15 ns 13 tDVWL Data Setup to WR Low 105 0.
Table 32-18 External Data Memory Characteristics, 2.7V - 5.5 V, SRWn1 = 1, SRWn0 = 1 Symbol 0 1/tCLCL Parameter 4MHz Oscillator Variable Oscillator Min Min Max 0.0 8 MHz 3.0tCLCL-60 ns Max Oscillator Frequency 690 Unit 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 735 3.0tCLCL-15 ns 14 tWHDX Data Hold After WR High 485 2.0tCLCL-15 ns 15 tDVWH Data Valid to WR High 750 3.0tCLCL ns 16 tWLWH WR Pulse Width 735 3.
Figure 32-9 External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 S ys te m Clock (CLKCP U ) 1 ALE 4 A15:8 7 Addre s s P rev. a ddr. 15 3a DA7:0 P rev. da ta 13 Addre s s Da ta XX 14 16 6 Write 2 WR 3b Addre s s Da ta 5 Re a d DA7:0 (XMBK = 0) 11 9 10 8 12 RD Figure 32-10 External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T5 T4 T6 S ys te m Clock (CLKCP U ) 1 ALE 4 A15:8 7 Addre s s P rev. a ddr. 15 3a DA7:0 P rev.
Figure 32-11 External Memory Timing (SRWn1 = 1, SRWn0 = 1) T1 T2 T3 T4 T6 T5 T7 S ys te m Clock (CLKCP U ) 1 ALE 4 A15:8 7 Addre s s P rev. a ddr. 15 3a DA7:0 P rev. da ta Addre s s 13 Da ta XX 14 16 6 Write 2 WR 9 3b Addre s s 11 Da ta 5 Re a d DA7:0 (XMBK = 0) 10 8 12 RD The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external).
33. Electrical Characteristics – TA = -40°C to 105°C Table 33-1 Absolute Maximum Ratings* 33.1. Operating Temperature -55°C to +125°C Storage Temperature -65°C to +150°C Voltage on any Pin except RESET with respect to Ground -0.5V to VCC+0.5V Voltage on RESET with respect to Ground -0.5V to +13.0V Maximum Operating Voltage 6.0V DC Current per I/O Pin 40.0mA DC Current VCC and GND Pins 200.0 - 400.
Symbol Parameter Condition IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1.0 IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) 1.0 RRST Reset Pull-up Resistor 30 60 RPEN PEN Pull-up Resistor 30 60 RPU I/O Pin Pull-up Resistor 20 50 Power Supply Current ICC Power-down mode(5) Min Typ Max Active 4MHz, VCC = 3V 2.5 5 Active 8MHz, VCC = 5V 8.1 20 Idle 4MHz, VCC = 3V 0.7 2 Idle 8MHz, VCC = 5V 2.
5. 5. The sum of all IOH, for ports F0 - F7, should not exceed 100mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. Minimum VCC for Power-down is 2.5V.
34. Typical Characteristics – TA = -40°C to 85°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
Figure 34-2 Active Supply Current vs. Frequency (1 - 16 MHz) ACTIVE S UP P LY CURRENT vs . FREQUENCY 1 - 16 MHz 20 5.5 V 16 5.0 V ICC (mA) 4.5 V 12 4.0 V 3.6 V 8 3.3 V 4 2.7 V 0 0 2 4 6 8 10 12 14 16 Fre que ncy (MHz) Figure 34-3 Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR. 1 MHz 2.4 85 25 0 -40 2.2 °C °C °C °C ICC (mA) 2 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 5.
Figure 34-4 Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 2 MHz 4.5 -40 °C 25 °C 85 °C 4 ICC (mA) 3.5 3 2.5 2 1.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-5 Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 4 MHz 7 -40 °C 25 °C 85 °C ICC (mA) 6 5 4 3 2 2.5 3 3.5 4 4.5 5 5.
Figure 34-6 Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 8 MHz 12 -40 °C 25 °C 85 °C 11 10 ICC (mA) 9 8 7 6 5 4 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-7 Active Supply Current vs. VCC (32 kHz External Oscillator) ACTIVE S UP P LY CURRENT vs . VCC EXTERNAL RC OS CILLATOR, 32 kHz 90 25 °C ICC (mA) 80 70 60 50 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 34-8 Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz 0.6 5.5 V 0.5 5.0 V 4.5 V ICC (mA) 0.4 4.0 V 3.6 V 0.3 3.3 V 2.7 V 0.2 0.1 0 0.1 0.2 0.3 0.4 0,5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Figure 34-9 Idle Supply Current vs. Frequency (1 - 16 MHz) IDLE S UP P LY CURRENT vs . FREQUENCY 1 - 16 MHz 8 5.5 V 7 5.5 V 6 5.5 V 5 ICC (mA) 34.2. 5.5 V 4 3.6 V 3 3.3 V 2 2.
Figure 34-10 Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 1 MHz 0.7 85 °C 25 °C -40 °C ICC (mA) 0.6 0.5 0.4 0.3 0,2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-11 Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 2 MHz 1.2 85 °C 25 °C -40 °C ICC (mA) 1 0.8 0.6 0,4 2.5 3 3.5 4 4.5 5 5.
Figure 34-12 Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 4 MHz 2.6 -40 °C 25 °C 85 °C ICC (mA) 2.2 1.8 1.4 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-13 Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 8 MHz 5 -40 °C 25 °C 85 °C 4.5 ICC (mA) 4 3.5 3 2.5 2 1.5 2.5 3 3.5 4 4.5 5 5.
Figure 34-14 Idle Supply Current vs. VCC (32 kHz External Oscillator) IDLE S UP P LY CURRENT vs . VCC EXTERNAL RC OS CILLATOR, 32 kHz 30 25 25 °C ICC (mA) 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-Down Supply Current Figure 34-15 Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) P OWER-DOWN S UP P LY CURRENT vs . VCC WATCHDOG TIMER DIS ABLED 3.5 85 °C 3 2.5 ICC (uA) 34.3. 2 -40 °C 25 °C 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 34-16 Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) P OWER-DOWN S UP P LY CURRENT vs . VCC WATCHDOG TIMER ENABLED 25 85 °C 25 °C -40 °C ICC (uA) 21 17 13 9 5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-Save Supply Current Figure 34-17 Power-Save Supply Current vs. VCC (Watchdog Timer Disabled) P OWER-S AVE S UP P LY CURRENT vs . VCC WATCHDOG TIMER DIS ABLED 12 25 °C 11 10 ICC (uA) 34.4. 9 8 7 6 5 2.5 3 3.5 4 4.5 5 5.
Standby Supply Current Figure 34-18 Standby Supply Current vs. VCC S TANDBY S UP P LY CURRENT vs . VCC 0.16 6MHz Xta l 0.14 6MHz Re s ICC (mA) 0.12 4MHz Re s 4MHz Xta l 0.1 2MHz Re s 2MHz Xta l 0.08 450kHz Re s 1MHz Re s 0.06 0.04 0.02 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-19 Standby Supply Current vs. VCC (CKOPT Programmed) S TANDBY S UP P LY CURRENT vs . VCC CKOP T P rogra mme d 2 16MHz Xta l 1.6 ICC (mA) 34.5. 12MHz Xta l 1.2 6MHz Xta l 4MHz Xta l 0.8 0.4 0 2.5 3 3.
Pin Pull-up Figure 34-20 I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE Vcc = 5V 140 120 IOP (uA) 100 80 60 40 25 °C -40 °C 85 °C 20 0 0 1 2 3 4 5 6 VOP (V) Figure 34-21 I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE Vcc = 2.7V 80 70 60 50 IOP (uA) 34.6. 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.
Figure 34-22 Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vcc = 5V 120 100 IRES ET (uA) 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRES ET (V) Figure 34-23 Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vcc = 2.7V 60 50 IRES ET (uA) 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.
Figure 34-24 PEN Pull-up Resistor Current vs. PEN Pin Voltage (VCC = 5V) P EN P ULL-UP RES IS TOR CURRENT vs . P EN P IN VOLTAGE VCC = 5V 140 120 IP EN (uA) 100 80 60 40 25 °C 85 °C -40 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VP EN (V) Figure 34-25 PEN Pull-up Resistor Current vs. PEN Pin Voltage (VCC = 2.7V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vcc = 2.7V 60 50 IRES ET (uA) 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.
Pin Driver Strength Figure 34-26 I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O P IN S OURCE CURRENT vs . OUTP UT VOLTAGE Vcc = 5V 90 80 70 IOH (mA) 60 50 40 30 20 -40 °C 25 °C 85 °C 10 0 3 3.4 3.8 4.2 4.6 5 VOH (V) Figure 34-27 I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O P IN S OURCE CURRENT vs . OUTP UT VOLTAGE Vcc = 2.7V 35 30 25 IOH (mA) 34.7. 20 15 10 -40 °C 25 °C 85 °C 5 0 0.5 1 1.5 2 2.
Figure 34-28 I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O P IN S INK CURRENT vs . OUTP UT VOLTAGE Vcc = 5V 90 -40 °C 80 25 °C 70 85 °C IOL (mA) 60 50 40 30 20 10 0 0 0.4 0.8 1.2 1.6 2 VOL (V) Figure 34-29 I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I/O P IN S INK CURRENT vs . OUTP UT VOLTAGE Vcc = 2.7V 35 -40 °C 30 25 °C IOL (mA) 25 85 °C 20 15 10 5 0 0 0.4 0.8 1.2 1.
Pin Thresholds and Hysteresis Figure 34-30 I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as '1') I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC VIH, IO P IN READ AS '1' 3 85 °C 25 °C -40 °C Thre s hold (V) 2.6 2.2 1.8 1.4 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-31 I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as '0') I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC VIL, IO P IN READ AS '0' 2.5 -40 °C 85 °C 25 °C 2.2 Thre s hold (V) 34.8. 1.9 1.6 1.3 1 2.5 3 3.
Figure 34-32 I/O Pin Input Hysteresis vs. VCC I/O P IN INP UT HYS TERES IS vs . VCC 0.8 85 °C 25 °C -40 °C Input Hys te re s is (mV) 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-33 Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as '1') RES ET INP UT THRES HOLD VOLTAGE vs . VCC VIH, IO P IN READ AS '1' 2.4 -40 °C 25 °C 85 °C 2.2 Thre s hold (V) 2 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 5.
Figure 34-34 Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as '0') RES ET INP UT THRES HOLD VOLTAGE vs . VCC VIL, IO P IN READ AS '0' 2.4 -40 °C 25 °C 85 °C 2.2 Thre s hold (V) 2 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-35 Reset Input Pin Hysteresis vs. VCC RES ET INP UT P IN HYS TERES IS vs . VCC 0.5 Input Hys te re s is (mV) 0.4 0.3 0.2 0.1 -40 °C 25 °C 85 °C 0 2.5 3 3.5 4 4.5 5 5.
BOD Thresholds and Analog Comparator Offset Figure 34-36 BOD Thresholds vs. Temperature (BODLEVEL is 4.0V) BOD THRES HOLDS vs . TEMP ERATURE BOD LEVEL IS 4.0 V 4.2 Ris ing Vcc Thre s hold (V) 4.15 4.1 4.05 Fa lling Vcc 4 3.95 -40 -25 -10 5 20 35 50 65 80 95 80 95 Te mpe ra ture (°C ) Figure 34-37 BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) BOD THRES HOLDS vs . TEMP ERATURE BOD LEVEL IS 2.7 V 2.76 Ris ing Vcc 2.73 2.7 Thre s hold (V) 34.9. 2.67 2.64 Fa lling Vcc 2.61 2.
Figure 34-38 Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs . VCC 1.215 85 °C 25 °C Ba ndga p Volta ge (V) 1.21 1.205 -40 °C 1.2 1.195 1.19 1.185 1.18 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 34.10. Internal Oscillator Speed Figure 34-39 Watchdog Oscillator Frequency vs. VCC WATCHDOG OS CILLATOR FREQUENCY vs . Vcc 1180 25 °C -40 °C 85 °C 1160 F RC (kHz) 1140 1120 1100 1080 1060 1040 2.5 3 3.5 4 4.5 5 5.
Figure 34-40 Calibrated 1 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 1MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 1.02 1 F RC (MHz) 5.5 V 0.98 5.0 V 4.5 V 0.96 4.0 V 3.6 V 3.3 V 0.94 2.7 V 0.92 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Te mpe ra ture (°C ) Figure 34-41 Calibrated 1 MHz RC Oscillator Frequency vs. VCC CALIBRATED 1MHz RC OS CILLATOR FREQUENCY vs . Vcc 1.02 -40 °C 25 °C 1 F RC (MHz) 85 °C 0.98 0.96 0.94 0.92 2.5 3 3.5 4 4.5 5 5.
Figure 34-42 Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 1MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 1.8 25 °C 1.6 F RC (MHz) 1.4 1.2 1 0.8 0.6 0.4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OS CCAL VALUE Figure 34-43 Calibrated 2 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 2MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 2.05 2 F RC (MHz) 5.5 V 5.0 V 1.95 4.5 V 4.0 V 1.9 3.6 V 3.3 V 3.0 V 1.85 2.7 V 1.
Figure 34-44 Calibrated 2 MHz RC Oscillator Frequency vs. VCC CALIBRATED 2MHz RC OS CILLATOR FREQUENCY vs . Vcc 2.05 -40 °C 25 °C 2 F RC (MHz) 85 °C 1.95 1.9 1.85 1.8 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-45 Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 2MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 3.6 25 °C 3.2 F RC (MHz) 2.8 2.4 2 1.6 1.2 0.
Figure 34-46 Calibrated 4 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 4.1 4 5.5 V 5.0 V F RC (MHz) 3.9 4.5 V 4.0 V 3.8 3.6 V 3.3 V 3.7 2.7 V 3.6 3.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Te mpe ra ture (°C ) Figure 34-47 Calibrated 4 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4MHz RC OS CILLATOR FREQUENCY vs . Vcc 4.1 -40 °C 25 °C 4 85 °C F RC (MHz) 3.9 3.8 3.7 3.6 3.5 2.5 3 3.5 4 4.5 5 5.
Figure 34-48 Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 8 25 °C 7 F RC (MHz) 6 5 4 3 2 1 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OS CCAL VALUE Figure 34-49 Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 8.4 8.2 8 5.5 V 5.0 V 4.5 V F RC (MHz) 7.8 7.6 7.4 4.0 V 7.2 3.6 V 3.3 V 7 6.8 2.7 V 6.6 6.
Figure 34-50 Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . Vcc 8.4 -40 °C 8.2 25 °C 8 85 °C F RC (MHz) 7.8 7.6 7.4 7.2 7 6.8 6.6 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-51 Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs .
34.11. Current Consumption of Peripheral Units Figure 34-52 Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs . VCC 20 -40 °C 18 25 °C 16 ICC (uA) 85 °C 14 12 10 8 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-53 ADC Current vs. VCC (ADC CLK = 50 kHz) ADC CURRENT vs . VCC ADC CLK = 50 KHz 375 25 °C 85 °C 350 -40 °C ICC (uA) 325 300 275 250 225 200 2.5 3 3.5 4 4.5 5 5.
Figure 34-54 Aref Current vs. VCC AREF CURRENT vs . VCC ADC CLK = 1 MHz 200 25 °C 85 °C -40 °C ICC (uA) 175 150 125 100 75 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-55 Analog Comparator Current vs. VCC ANALOG COMP ARATOR CURRENT vs . VCC 70 85 °C 65 60 25 °C ICC (uA) 55 -40 °C 50 45 40 35 30 2.5 3 3.5 4 4.5 5 5.
Figure 34-56 Programming Current vs. VCC P ROGRAMMING CURRENT vs . Vcc Ext Clk 8 -40 °C ICC (mA) 7 6 25 °C 5 85 °C 4 3 2 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.12. Current Consumption in Reset and Reset Pulse width Figure 34-57 Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the Reset Pull-up) RES ET S UP P LY CURRENT vs . VCC 0.1 - 1.0 MHz EXCLUDING CURRENT THROUGH THE RES ET P ULLUP 3 5.5 V 2.5 5.0 V 4.5 V ICC (mA) 2 4.0 V 3.6 V 3.3 V 1.5 2.7 V 1 0.5 0 0.
Figure 34-58 Reset Supply Current vs. VCC (1 - 16 MHz, Excluding Current through the Reset Pull-up) RES ET S UP P LY CURRENT vs . VCC 1 - 16 MHz EXCLUDING CURRENT THROUGH THE RES ET P ULLUP 16 5.5 V 5.0 V 12 ICC (mA) 4.5 V 4.0 V 8 3.6 V 3.3 V 4 2.7 V 0 0 2 4 6 8 10 12 14 16 Fre que ncy (MHz) Figure 34-59 Minimum Reset Pulse Width vs. VCC MINIMUM RES ET P ULS E WIDTH vs . VCC 800 P uls e width (ns ) 600 400 85 °C 25 °C -40 °C 200 0 2.5 3 3.5 4 4.5 5 5.
35. Typical Characteristics – TA = -40°C to 105°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
Figure 35-2 Active Supply Current vs. Frequency (1 - 16MHz) ACTIVE S UP P LY CURRENT vs . FREQUENCY 1 - 16 MHz 20 5.5V ICC (mA) 18 16 5.0V 14 4.5V 12 4.0V 10 3.6V 8 3.3V 6 2.7V 4 2 0 0 2 4 6 8 10 12 14 16 Fre que ncy (MHz) Figure 35-3 Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 8 MHz -40°C 25°C 85°C 105°C 12 11 10 ICC (mA) 9 8 7 6 5 4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 35-4 Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 4 MHz 7.0 -40°C 25°C 85°C 105°C 6.5 6.0 ICC (mA) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 35-5 Active Supply Current vs. VCC (Internal RC Oscillator, 2MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 2 MHz 4.5 -40°C 25°C 85°C 105°C 4.0 ICC (mA) 3.5 3.0 2.5 2.0 1.5 2.5 2.8 3.1 3.4 3.7 4 4.
Figure 35-6 Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 1 MHz 2.5 105°C 85°C 25°C -40°C 2.3 ICC (mA) 2.1 1.9 1.7 1.5 1.3 1.1 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Idle Supply Current Figure 35-7 Idle Supply Current vs. Frequency (0.1 - 1.0MHz) IDLE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz 0.59 5.5V 0.53 5.0V 0.47 4.5V 0.41 ICC (mA) 35.2. 0.29 4.0V 3.6V 3.3V 0.23 2.7V 0.35 0.17 0.
Figure 35-8 Idle Supply Current vs. Frequency (1 - 16MHz) IDLE S UP P LY CURRENT vs . FREQUENCY 1 - 16 MHZ 8 5.5V 7 5.0V 6 4.5V ICC (mA) 5 4.0V 4 3.6V 3 3.3V 2 2.7V 1 0 0 2 4 6 8 10 12 14 16 Fre que ncy (MHz) Figure 35-9 Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 8 MHz -40°C 25°C 85°C 105°C 5.1 4.6 ICC (mA) 4.1 3.6 3.1 2.6 2.1 1.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 35-10 Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 4 MHz 2.8 -40°C 25°C 85°C 105°C 2.5 ICC (mA) 2.2 1.9 1.6 1.3 1.0 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 35-11 Idle Supply Current vs. VCC (Internal RC Oscillator, 2MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 2 MHz 105°C 85°C 25°C -40°C 1.23 1.13 1.03 ICC (mA) 0.93 0.83 0.73 0.63 0.53 0.43 2.5 2.8 3.1 3.4 3.7 4 4.
Figure 35-12 Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 1 MHz 105°C 85°C 25°C -40°C 0.74 0.68 0.62 ICC (mA) 0.56 0.5 0.44 0.38 0.32 0.26 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Power-down Supply Current Figure 35-13 Power-down Supply Current vs. VCC (Watchdog Timer Disabled) P OWER-DOWN S UP P LY CURRENT vs . VCC WATCHDOG TIMER DIS ABLED 6 105°C 5 4 ICC (µA) 35.3. 3 85°C 2 -40°C 25°C 1 0 2.5 2.8 3.
Figure 35-14 Power-down Supply Current vs. VCC (Watchdog Timer Enabled) P OWER-DOWN S UP P LY CURRENT vs . VCC WATCHDOG TIMER ENABLED 105°C 27 25 85°C 25°C -40°C 23 ICC (µA) 21 19 17 15 13 11 9 7 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Pin Pull-up Figure 35-15 I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE VCC = 5V 140 120 100 IOP (µA) 35.4. 80 60 40 25°C 85°C 105°C -40°C 20 0 0 0.5 1 1.5 2 2.
Figure 35-16 I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE VCC = 2.7V 80 70 60 IOP (µA) 50 40 30 20 25°C 85°C -40°C 105°C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VOP (V) Figure 35-17 Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 120 105 I RESET (μA) 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 35-18 Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 60 I RESET(μA) 50 40 30 20 25°C -40°C 85°C 105°C 10 0 0 0.3 0.6 0.9 1.5 1.2 1.8 2.1 2.7 2.4 VRESET (V) Pin Driver Strength Figure 35-19 I/O Pin Output Voltage vs. Source Current, Port B (VCC= 5V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT VCC = 5V 5 4.9 4.8 VOH (V) 35.5. 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 105°C 4.
Figure 35-20 I/O Pin Output Voltage vs. Source Current, Port B (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT NORMAL P OWER P INS 3.1 2.9 VOH (V) 2.7 2.5 -40°C 2.3 25°C 2.1 85°C 105°C 1.9 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 35-21 I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT VCC = 5V VOL (V) 0.7 0.6 105°C 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.
Figure 35-22 I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT VCC = 3V 1.0 105°C 85°C 0.9 0.8 25°C VOL (V) 0.7 0.6 -40°C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Pin Thresholds and Hysteresis Figure 35-23 I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC VIH, IO P IN READ AS '1' 25°C 105°C 85°C -40°C 3.1 2.9 2.7 Thre s hold (V) 35.6. 2.5 2.3 2.1 1.9 1.
Figure 35-24 I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC VIL, IO P IN READ AS '0' 105°C 85°C 25°C -40°C 2.4 2.2 Thre s hold (V) 2 1.8 1.6 1.4 1.2 1 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 35-25 I/O Pin Input Hysteresis vs. VCC I/O P IN INP UT HYS TERES IS vs . VCC 0.65 105°C 85°C 25°C 0.60 -40°C Input Hys te re s is (mV) 0.70 0.55 0.50 0.45 0.40 0.35 0.30 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.
Figure 35-26 Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) Reset Input Threshold Voltage vs. Vcc (VIH, Reset Pin Read as "1") 2.4 85°C 105°C Threshold (V) 2.2 2 1.8 -40°C 1.6 25°C 1.4 1.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 35-27 Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as "0") 105°C 85°C 25°C -40°C 2.4 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 2.5 2.8 3.1 3.4 3.
Figure 35-28 Reset Input Pin Hysteresis vs. VCC Reset Input Pin Hysteresis vs. VCC 0.5 0.45 Input Hysteresis (V) 0.4 0.35 0.3 0.25 0.2 0.15 0.1 -40°C 25°C 85°C 105°C 0.05 0 2.5 3.1 2.8 3.4 4 3.7 4.3 5.2 4.9 4.6 5.5 VCC (V) BOD Thresholds and Analog Comparator Offset Figure 35-29 BOD Thresholds vs. Temperature (BOD Level is 4.3V) BOD THRES HOLDS vs . TEMP ERATURE 3.915 Ris ing Vcc 3.895 3.875 Thre s hold (V) 35.7. 3.855 3.835 3.815 3.795 Fa lling Vcc 3.775 3.
Figure 35-30 BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRES HOLDS vs . TEMP ERATURE 2.735 Ris ing Vcc 2.715 Thre s hold (V) 2.695 2.675 2.655 2.635 Fa lling Vcc 2.615 2.595 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Te mpe ra ture ( °C) Figure 35-31 Bandgap Voltage vs. Temperature BANDGAP VOLTAGE vs . TEMP ERATURE 1.201 1.196 Ba ndga p Volta ge (V) 1.191 5.5V 1.186 1.181 1.176 5.0V 1.171 1.166 4.5V 2.7V 1.
Internal Oscillator Speed Figure 35-32 Watchdog Oscillator Frequency vs. VCC WATCHDOG OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 1220 -40°C 25°C 1200 85°C 105°C F RC (kHz) 1180 1160 1140 1120 1100 1080 1060 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 35-33 Watchdog Oscillator Frequency vs. Temperature WATCHDOG OS CILLATOR FREQUENCY vs . TEMP ERATURE 1220 1200 5.5V 1180 F RC (kHz) 35.8. 1160 1140 5.0V 1120 4.5V 1100 4.0 V 3.6 V 3.3 V 1080 2.
Figure 35-34 Calibrated 1MHz RC Oscillator Frequency vs. Temperature Calibrated 1MHz RC Oscillator Frequency vs. Temperature 1.03 1.01 FRC (MHz) 0.99 5.5V 0.97 5.0V 4.5V 0.95 4.0V 3.6V 3.3V 0.93 0.91 -45 -35 -25 -15 2.7V -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 35-35 Calibrated 1MHz RC Oscillator Frequency vs. VCC Calibrated 1MHz RC Oscillator Frequency vs. VCC 1.03 -40°C 1.015 25°C FRC (MHz) 1 85°C 105°C 0.985 0.97 0.955 0.94 0.925 0.91 2.5 2.8 3.1 3.4 3.
Figure 35-36 Calibrated 2MHz RC Oscillator Frequency vs. Temperature Calibrated 2MHz RC Oscillator Frequency vs. Temperature 2.09 2.04 FRC (MHz) 1.99 5.5V 5.0V 4.5V 4.0V 3.6V 3.3V 1.94 1.89 1.84 1.79 -45 -35 -25 -15 2.7V -5 5 15 45 35 25 55 65 75 85 95 105 Temperature (°C) Figure 35-37 Calibrated 2MHz RC Oscillator Frequency vs. VCC Calibrated 2MHz RC Oscillator Frequency vs. VCC 2.08 -40°C 2.04 25°C FRC (MHz) 2 85°C 105°C 1.96 1.92 1.88 1.84 1.8 2.5 2.8 3.1 3.4 3.7 4 4.3 4.
Figure 35-38 Calibrated 4MHz RC Oscillator Frequency vs. Temperature Calibrated 4MHz RC Oscillator Frequency vs. Temperature 4.15 FRC (MHz) 4.05 3.95 5.5V 5.0V 4.5V 4.0V 3.6V 3.3V 3.85 3.75 3.65 2.7V 3.55 -45 -35 -25 -15 -5 5 15 45 35 25 55 75 65 85 95 105 Temperature (°C) Figure 35-39 Calibrated 4MHz RC Oscillator Frequency vs. VCC Calibrated 4MHz RC Oscillator Frequency vs. VCC 4.15 -40°C FRC (MHz) 4.05 25°C 3.95 85°C 105°C 3.85 3.75 3.65 3.55 2.5 2.8 3.1 3.4 3.7 4 4.3 4.
Figure 35-40 Calibrated 8MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 8.4 8.2 8.0 F RC (MHz) 7.8 7.0 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 6.8 3.0 V 7.6 7.4 7.2 2.7 V 6.6 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Te mpe ra ture (°C) Figure 35-41 Calibrated 8MHz RC Oscillator Frequency vs. VCC CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 8.5 -40°C 8.2 25°C F RC (MHz) 7.9 85°C 105°C 7.
Figure 35-42 Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value 16 -40°C 25°C 85°C 105°C 14 FRC (MHz) 12 10 8 6 4 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Current Consumption of Peripheral Units Figure 35-43 Brownout Detector Current vs. VCC Brownout Detector Current vs. VCC 19 -40°C 18 25°C 17 16 I CC (µA) 35.9. 85°C 105°C 15 14 13 12 11 10 9 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.
Figure 35-44 ADC Current vs. VCC (AREF = AVCC) ADC Current vs. VCC (AREF = AVCC) 420 105°C 85°C 25°C -40°C 400 380 I CC (µA) 360 340 320 300 280 260 240 220 2.5 2.8 3.1 3.4 4 3.7 4.3 4.9 4.6 5.2 5.5 VCC (V) Figure 35-45 AREF External Reference Current vs. VCC AREF External Reference Current vs. VCC 190 105°C 85°C 25°C -40°C 180 170 I CC (µA) 160 150 140 130 120 110 100 90 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 35-46 Watchdog Timer Current vs. VCC Watchdog Timer Current vs. VCC 21 105°C 85°C 25°C -40°C 19 I CC (µA) 17 15 13 11 9 7 5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Figure 35-47 Analog Comparator Current vs. VCC Analog Comparator Current vs. VCC 85 85°C 80 75 105°C 70 25°C I CC (µA) 65 -40°C 60 55 50 45 40 35 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
Figure 35-48 Programming Current vs. VCC Programming Current vs. VCC 6 -40°C 5.5 I CC (mA) 5 4.5 25°C 4 85°C 105°C 3.5 3 2.5 2 1.5 1 2.5 2.8 3.1 3.4 3.7 4.3 4 4.9 4.6 5.2 5.5 VCC (V) 35.10. Current Consumption in Reset and Reset Pulsewidth Figure 35-49 Reset Supply Current vs. VCC (0.1 - 1.0 Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) 3 5.5V 2.7 5.0V 2.4 4.5V I CC (mA) 2.1 1.5 4.0V 3.6V 3.3V 1.2 2.7V 1.8 0.9 0.6 0.3 0 0.1 0.2 0.
Figure 35-50 Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through The Reset Pull-up) Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through The Reset Pull-up) 16 5.5V 14 5.0V 12 4.5V I CC (mA) 10 4.0V 8 3.6V 6 3.3V 4 2.7V 2 0 0 6 4 2 8 10 12 14 16 Figure 35-51 Minimum Reset Pulse Width vs. VCC Minimum Reset Pulse Width vs. VCC 800 Pulsewidth (ns) 700 600 500 400 105°C 85°C 25°C 300 200 2.5 -40°C 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.
36.
Address Name Bit 7 Bit 6 Bit 5 (0x74) TWCR TWINT TWEA TWSTA (0x73) TWDR (0x72) TWAR TWA6 TWA5 TWA4 (0x71) TWSR TWS7 TWS6 TWS5 (0x70) TWBR Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TWSTO TWWC TWEN – TWIE Two-wire Serial Interface Data Register TWA3 TWA2 TWA1 TWA0 TWGCE TWS4 TWS3 – TWPS1 TWPS0 Two-wire Serial Interface Bit Rate Register (0x6F) OSCCAL (0x6E) Reserved – – – Oscillator Calibration Register – – – – – (0x6D) XMCRA – SRL2 SRL1 SRL0 SRW01 SRW00 SR
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x25 (0x45) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 0x24 (0x44) TCNT2 Timer/Counter2 (8 Bit) 0x23 (0x43) OCR2 Timer/Counter2 Output Compare Register 0x22 (0x42) OCDR 0x21 (0x41) WDTCR IDRD/ OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 – – – WDCE WDE WDP2 WDP1 WDP0 ACME PUD PSR0 PSR321 OCDR7 0x20 (0x40) SFIOR TSM – – – 0x1F (0x3F) EEARH – – – – EEPROM Address Register High 0x1E
37.
BRANCH INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks Indirect Call to (Z) PC ← Z None 3 Direct Subroutine Call PC ← k None 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 ICALL CALL(1) k CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd - Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd - K Z, N,V,C,
BIT AND BIT-TEST INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C¬Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0:6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3:0)←Rd(7:4),Rd(7:4)¬Rd(3
DATA TRANSFER INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec.
MCU CONTROL INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Note: 1. Instruction not available in all devices.
38. Packaging Information 38.1. 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° L A1 A2 A COMMON DIMENSIONS (Unit of measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.
38.2. 64M1 D Ma rked Pin# 1 I D E C SE ATING PLAN E A1 TOP VIE W A K 0.08 L Pin #1 Co rne r D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B K Option C b C e BOTTOM VIE W Notes: Pin #1 Cham fe r (C 0.30) Pin #1 Notch (0.20 R) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 b 0.18 0.25 0.30 D 8.90 9.00 9.10 D2 5.20 5.40 5.60 E 8.90 9.00 9.10 E2 5.20 5.40 5.60 e NOTE 0.50 BSC L 0.35 0.40 0.
39. Errata The revision letter in this section refers to the revision of the ATmega64A device. 39.1. ATmega64A Rev. D • • • • • • First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer Stabilizing time needed when changing XDIV Register Stabilizing time needed when changing OSCCAL Register IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1.
NOP NOP NOP NOP NOP SEI 4. ; ; ; ; ; ; no operation no operation no operation no operation no operation set global interrupt enable Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device may execute some of the subsequent instructions incorrectly. Problem Fix/Workaround 5. The behavior follows errata number 3., and the same Fix / Workaround is applicable on this errata.
40. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section refers to the document revision. 40.1. 8160E - 07/2015 1. 40.2. 8160D - 02/2013 1. 2. 3. 4. 5. 6. 7. 8. 40.3. Updated Errata on page 502. 8160B - 03/2009 1. 2. 3. 40.5. Applied the new template that includes new logo and new last page. Added Capacitive Touch Sensing on page 21. Note is added Performing Page Erase by SPM on page 373.
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