Datasheet

Figure 29-3. SPI Interface Timing Requirements (Master Mode)
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
6 1
2 2
34 5
87
Figure 29-4. SPI Interface Timing Requirements (Slave Mode)
MISO
(Data Output)
SCK
(CPOL = 1)
MOSI
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
10
11 11
1213 14
1715
9
X
16
29.8. Two-wire Serial Interface Characteristics
The table in this section describes the requirements for devices connected to the 2-wire Serial Bus. The
2-wire Serial Interface meets or exceeds these requirements under the noted conditions.
The timing symbols refers to Figure 29-5.
Table 29-11. Two-wire Serial Bus Requirements
Symbol Parameter Condition Min. Max Units
V
IL
Input Low-voltage -0.5 0.3 V
CC
V
V
IH
Input High-voltage 0.7 V
CC
V
CC
+ 0.5 V
V
hys
(1)
Hysteresis of Schmitt Trigger
Inputs
0.05 V
CC
(2)
– V
Atmel ATmega644PA [DATASHEET]
Atmel-42717C-ATmega644PA_Datasheet_Complete-10/2016
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