Datasheet
29.7. SPI Timing Characteristics
Table 29-10. SPI Timing Parameters
Description Mode Min. Typ Max Units
SCK period Master - See Table. Relationship Between SCK and the
Oscillator Frequency in "SPCR – SPI Control Register"
- ns
SCK high/low Master - 50% duty cycle -
Rise/Fall time Master - 3.6 -
Setup Master - 10 -
Hold Master - 10 -
Out to SCK Master - 0.5 • t
sck
-
SCK to out Master - 10 -
SCK to out high Master - 10 -
SS low to out Slave - 15 -
SCK period Slave 4 • t
ck
- -
SCK high/low
(1)
Slave 2 • t
ck
- -
Rise/Fall time Slave - - 1600
Setup Slave 10 - -
Hold Slave t
ck
- -
SCK to out Slave - 15 -
SCK to SS high Slave 20 - -
SS high to tri-state Slave - 10 -
SS low to SCK Slave 2 • t
ck
- -
Note:
1. In SPI Programming mode the minimum SCK high/low period is:
• 2 t
CLCL
for f
CK
< 12MHz
• 3 t
CLCL
for f
CK
> 12MHz
Atmel ATmega644PA [DATASHEET]
Atmel-42717C-ATmega644PA_Datasheet_Complete-10/2016
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