Datasheet

26.16.2. MCU Control Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: MCUCR
Offset: 0x55
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x35
Bit 7 6 5 4 3 2 1 0
JTD BODS BODSE PUD IVSEL IVCE
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 – JTD
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one,
the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface,
a timed sequence must be followed when changing this bit: The application software must write this bit to
the desired value twice within four cycles to change its value. Note that this bit must not be altered when
using the On-chip Debug system.
Bit 6 – BODS: BOD Sleep
The BODS bit must be written to '1' in order to turn off BOD during sleep. Writing to the BODS bit is
controlled by a timed sequence and the enable bit BODSE. To disable BOD in relevant sleep modes, both
BODS and BODSE must first be written to '1'. Then, BODS must be written to '1' and BODSE must be
written to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS
is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared
after three clock cycles.
Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is
controlled by a timed sequence.
Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn
Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of
the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses.
To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to
change the IVSEL bit:
Atmel ATmega644PA [DATASHEET]
Atmel-42717C-ATmega644PA_Datasheet_Complete-10/2016
342