Datasheet

ManualsBrandsMicrochip ManualsAVR MicrocontrollersAVR RISC Microcontroller Flash 64KB TQFP

 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 1

Features

 High-performance, low-power 8-bit AVR

Microcontroller

 Advanced RISC architecture

 131 powerful Instructions – most single-clock cycle execution

 32 × 8 general purpose working registers

 Fully static operation

 Up to 20MIPS throughput at 20MHz

 On-chip 2-cycle multiplier

 High endurance non-volatile memory segments

 16/32/64/128KBytes of In-System Self-programmable Flash program memory

 512/1K/2K/4KBytes EEPROM

 1/2/4/16KBytes Internal SRAM

 Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM

 Data retention: 20 years at 85°C/ 100 years at 25°C

(1)

 Optional Boot Code Section with Independent Lock Bits

 In-System Programming by On-chip Boot Program

 True Read-While-Write Operation

 Programming Lock for Software Security

 QTouch

Library Support

 Capacitive touch buttons, sliders and wheels

 QTouch and QMatrix™ acquisition

 Up to 64 sense channels

 JTAG (IEEE std. 1149.1 Compliant) Interface

 Boundary-scan Capabilities According to the JTAG Standard

 Extensive On-chip Debug Support

 Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

ATmega164A/PA/324A/PA/644A/PA/1284/P

megaAVR

Data Sheet

Introduction

The ATmega164A/PA/324A/PA/644A/PA/1284/P is a low power, CMOS 8-bit microcontrollers based on the

AVR

enhanced RISC architecture. The ATmega164A/PA/324A/PA/644A/PA/1284/P is a 40/49-pins device

ranging from 16 KB to 128 KB Flash, with 1 KB to 16 KB SRAM, 512 Bytes to 4 KB EEPROM. By executing

instructions in a single clock cycle, the devices achieve CPU throughput approaching one million instruc-

tions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption ver-

sus processing speed.

Summary of content (662 pages)

PAGE 1
ATmega164A/PA/324A/PA/644A/PA/1284/P megaAVR® Data Sheet Introduction The ATmega164A/PA/324A/PA/644A/PA/1284/P is a low power, CMOS 8-bit microcontrollers based on the AVR® enhanced RISC architecture. The ATmega164A/PA/324A/PA/644A/PA/1284/P is a 40/49-pins device ranging from 16 KB to 128 KB Flash, with 1 KB to 16 KB SRAM, 512 Bytes to 4 KB EEPROM.
PAGE 2
ATmega164A/PA/324A/PA/644A/PA/1284/P  Peripheral Features  Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes  One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode  Real Time Counter with Separate Oscillator  Six PWM Channels  8-channel, 10-bit ADC  Differential mode with selectable gain at 1×, 10× or 200×  Byte-oriented Two-wire Serial Interface  Two Programmable Serial USART  Master/Slave SPI Serial Interface  Programmable Watch
PAGE 3
ATmega164A/PA/324A/PA/644A/PA/1284/P Table of Contents 1 2 Pin configurations ............................................................................................................... 11 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P 11 1.2 Pinout - DRQFN for ATmega164A/164PA/324A/324PA ................................. 12 1.3 Pinout - VFBGA for ATmega164A/164PA/324A/324PA .................................. 13 Overview ................................
PAGE 4
ATmega164A/PA/324A/PA/644A/PA/1284/P 9.3 Low Power Crystal Oscillator........................................................................... 41 9.4 Full swing Crystal Oscillator ............................................................................ 42 9.5 Low Frequency Crystal Oscillator .................................................................... 43 9.6 Calibrated Internal RC Oscillator ..................................................................... 44 9.
PAGE 5
ATmega164A/PA/324A/PA/644A/PA/1284/P 14 I/O-Ports ..................................................................................................................................... 80 14.1 Overview.......................................................................................................... 80 14.2 Ports as General Digital I/O ............................................................................. 81 14.3 Alternate Port Functions ....................................................
PAGE 6
ATmega164A/PA/324A/PA/644A/PA/1284/P 17.7 Modes of operation........................................................................................ 151 17.8 Timer/Counter Timing diagrams .................................................................... 155 17.9 Asynchronous Operation of Timer/Counter2 ................................................. 156 17.10 Timer/Counter Prescaler ............................................................................... 158 17.11 Register description .
PAGE 7
ATmega164A/PA/324A/PA/644A/PA/1284/P 21.2 Two-wire Serial Interface bus definition......................................................... 211 21.3 Data Transfer and Frame Format .................................................................. 212 21.4 Multi-master Bus Systems, Arbitration and Synchronization ......................... 214 21.5 Overview of the TWI Module ......................................................................... 217 21.6 Using the TWI...............................
PAGE 8
ATmega164A/PA/324A/PA/644A/PA/1284/P 25.2 Overview........................................................................................................ 268 25.3 Data Registers............................................................................................... 269 25.4 Boundary-scan Specific JTAG Instructions ................................................... 270 25.5 Boundary-scan Chain .................................................................................... 271 25.
PAGE 9
ATmega164A/PA/324A/PA/644A/PA/1284/P 28.7 Two-wire Serial Interface Characteristics ...................................................... 336 28.8 ADC characteristics ....................................................................................... 338 29 Electrical Characteristics - TA = -40°C to 105°C ............................................. 341 29.1 DC Characteristics.........................................................................................
PAGE 10
ATmega164A/PA/324A/PA/644A/PA/1284/P 35.5 36 Errata 49C2 ............................................................................................................. 655 ......................................................................................................................................... 656 36.1 Errata for ATmega164A................................................................................. 656 36.2 Errata for ATmega164PA .....................................................
PAGE 11
ATmega164A/PA/324A/PA/644A/PA/1284/P 1. Pin configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 1-1.
PAGE 12
ATmega164A/PA/324A/PA/644A/PA/1284/P Pinout - DRQFN for ATmega164A/164PA/324A/324PA Figure 1-2. DRQFN - pinout Top view Bottom view A18 B1 B15 A17 B2 B14 B3 B4 A2 A3 A4 A5 B5 A18 A1 B15 A17 B1 B14 B2 A16 B13 A16 B13 B3 A15 B12 A15 A2 A3 A4 B4 A14 B12 A14 B11 A13 B11 A13 B5 A5 A6 A12 B10 A11 B9 A10 B8 A9 B7 A8 B6 A7 B8 A10 B9 A11 B10 A12 B7 A9 A8 B6 A6 Table 1-1. A24 B20 A23 B19 A22 B18 A21 B17 A20 B16 A19 A19 B16 A20 B17 A21 B18 A22 B19 A23 B20 A24 A1 A7 1.
PAGE 13
ATmega164A/PA/324A/PA/644A/PA/1284/P 1.3 Pinout - VFBGA for ATmega164A/164PA/324A/324PA Figure 1-3. VFBGA - pinout Top view 1 3 4 5 6 7 7 6 5 4 3 2 1 A A B B C C D D E E F F G G Table 1-2. 2.
PAGE 14
ATmega164A/PA/324A/PA/644A/PA/1284/P 2.1 Block diagram Figure 2-1. Block diagram PA7..0 PB7..0 VCC RESET GND Power Supervision POR / BOD & RESET PORT A (8) PORT B (8) Watchdog Timer Analog Comparator A/D Converter Watchdog Oscillator USART 0 XTAL1 Oscillator Circuits / Clock Generation EEPROM Internal Bandgap reference XTAL2 SPI 8bit T/C 0 CPU 16bit T/C 1 16bit T/C 1 JTAG/OCD 8bit T/C 2 TWI FLASH SRAM PORT C (8) TOSC2/PC7 TOSC1/PC6 USART 1 16bit T/C 3* PORT D (8) PD7..
PAGE 15
ATmega164A/PA/324A/PA/644A/PA/1284/P timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
PAGE 16
ATmega164A/PA/324A/PA/644A/PA/1284/P 2.3.3 Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated.
PAGE 17
ATmega164A/PA/324A/PA/644A/PA/1284/P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on www.microchip.com 4. About code examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details.
PAGE 18
ATmega164A/PA/324A/PA/644A/PA/1284/P 7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1.
PAGE 19
ATmega164A/PA/324A/PA/644A/PA/1284/P operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
PAGE 20
ATmega164A/PA/324A/PA/644A/PA/1284/P 7.3.1 SREG – Status Register(1) The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
PAGE 21
ATmega164A/PA/324A/PA/644A/PA/1284/P 7.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
PAGE 22
ATmega164A/PA/324A/PA/644A/PA/1284/P 7.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3.
PAGE 23
ATmega164A/PA/324A/PA/644A/PA/1284/P 7.5.1 SPH and SPL – Stack Pointer High and Stack pointer Low Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) – – – SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write Initial Value Note: 1.
PAGE 24
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 7-5. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.
PAGE 25
ATmega164A/PA/324A/PA/644A/PA/1284/P writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software.
PAGE 26
ATmega164A/PA/324A/PA/644A/PA/1284/P 7.7.1 Interrupt response time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During these four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
PAGE 27
ATmega164A/PA/324A/PA/644A/PA/1284/P 8. AVR memories 8.1 Overview This section describes the different memories in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 8.
PAGE 28
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 8-1. Program memory map Program Memory 0x0000 Application Flash Section Boot Flash Section 0x1FFF/0x3FFF/0x7FFF/0xFFFF 8.3 SRAM data memory Figure 8-2 shows how the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P SRAM Memory is organized. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions.
PAGE 29
ATmega164A/PA/324A/PA/644A/PA/1284/P The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 1024/2048/4096 bytes of internal data SRAM in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P are all accessible through all these addressing modes. The Register File is described in ”General Purpose Register File” on page 21. Figure 8-2.
PAGE 30
ATmega164A/PA/324A/PA/644A/PA/1284/P 8.4 EEPROM data memory The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P contains 512/1K/2K/4Kbytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
PAGE 31
ATmega164A/PA/324A/PA/644A/PA/1284/P 8.5 I/O memory The I/O space definition of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is shown in ”Register summary” on page 636. All ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space.
PAGE 32
ATmega164A/PA/324A/PA/644A/PA/1284/P 8.6 Register Description 8.6.
PAGE 33
ATmega164A/PA/324A/PA/644A/PA/1284/P different modes are shown in Table 8-1 on page 33. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 8-1. EEPROM Mode Bits EEPM1 EEPM0 Programming time Operation 0 0 3.4ms Erase and Write in one operation (Atomic Operation) 0 1 1.8ms Erase Only 1 0 1.
PAGE 34
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
PAGE 35
ATmega164A/PA/324A/PA/644A/PA/1284/P The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
PAGE 36
ATmega164A/PA/324A/PA/644A/PA/1284/P The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
PAGE 37
ATmega164A/PA/324A/PA/644A/PA/1284/P 8.6.4 GPIOR2 – General Purpose I/O Register 2 Bit 8.6.5 7 5 4 3 2 1 0 MSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LSB 4 3 2 1 GPIOR2 GPIOR1 – General Purpose I/O Register 1 Bit 8.6.
PAGE 38
ATmega164A/PA/324A/PA/644A/PA/1284/P 9. System clock and clock options 9.1 Clock systems and their distribution Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power management and sleep modes” on page 50. The clock systems are detailed below. Figure 9-1. Clock distribution.
PAGE 39
ATmega164A/PA/324A/PA/644A/PA/1284/P 9.1.3 Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 9.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a realtime counter even when the device is in sleep mode. 9.1.
PAGE 40
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 9-2. Number of Watchdog Oscillator Cycles Typical time-out (VCC = 5.0V) Typical time-out (VCC = 3.0V) Number of cycles 0ms 0ms 0 4.1ms 4.3ms 512 65ms 69ms 8K (8,192) Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual voltage and it will be required to select a delay longer than the Vcc rise time.
PAGE 41
ATmega164A/PA/324A/PA/644A/PA/1284/P 9.3 Low Power Crystal Oscillator This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. In these cases, refer to the ”Full swing Crystal Oscillator” on page 42. Some initial guidelines for choosing capacitors for use with crystals are given in Table 9-3.
PAGE 42
ATmega164A/PA/324A/PA/644A/PA/1284/P 2. 9.4 These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. Full swing Crystal Oscillator This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output.
PAGE 43
ATmega164A/PA/324A/PA/644A/PA/1284/P 9.5 Low Frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor.
PAGE 44
ATmega164A/PA/324A/PA/644A/PA/1284/P When this oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown in Table 9-9. Table 9-9. Start-up times for the Low Frequency Crystal Oscillator Clock Selection Start-up time from power-down and power-save Power conditions BOD enabled 1K CK Fast rising power 1K CK Slowly rising power 1K CK Additional delay from reset (VCC = 5.0V) 14CK (1) SUT1..0 0 00 (1) 0 01 (1) 0 10 0 11 14CK + 4.
PAGE 45
ATmega164A/PA/324A/PA/644A/PA/1284/P When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 9-11 on page 45. Table 9-11. Start-up times for the Internal Calibrated RC Oscillator clock selection Start-up time from powerdown and power-save Additional delay from reset (VCC = 5.0V) SUT1..0 BOD enabled 6CK 14CK 00 Fast rising power 6CK 14CK + 4.1ms 01 Slowly rising power 6CK 14CK + 65ms 10(1) Power conditions Reserved Note: 9.7 1.
PAGE 46
ATmega164A/PA/324A/PA/644A/PA/1284/P 9.8 External clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 9-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 9-4. External clock drive configuration NC XTAL2 EXTERNAL CLOCK SIGNAL XTAL1 GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-15. Table 9-14. Table 9-15.
PAGE 47
ATmega164A/PA/324A/PA/644A/PA/1284/P waveform output on the OC2B pin.” on page 163 for further description on selecting external clock as input instead of a 32.768kHz watch crystal. 9.10 Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system.
PAGE 48
ATmega164A/PA/324A/PA/644A/PA/1284/P 9.12 Register description 9.12.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
PAGE 49
ATmega164A/PA/324A/PA/644A/PA/1284/P is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 9-16.
PAGE 50
ATmega164A/PA/324A/PA/644A/PA/1284/P 10. Power management and sleep modes 10.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
PAGE 51
ATmega164A/PA/324A/PA/644A/PA/1284/P 10.3 BOD disable(1) When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 27-3 on page 296, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 10-1 on page 50. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses.
PAGE 52
ATmega164A/PA/324A/PA/644A/PA/1284/P 10.6 Power-down mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the two-wire Serial Interface, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, twowire Serial Interface address match, an external interrupt on INT2:0, or a pin change interrupt can wake up the MCU.
PAGE 53
ATmega164A/PA/324A/PA/644A/PA/1284/P 10.10 Power Reduction Register The Power Reduction Register (PRR), see ”PRR0 – Power Reduction Register 0” on page 56, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
PAGE 54
ATmega164A/PA/324A/PA/644A/PA/1284/P 10.11.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed.
PAGE 55
ATmega164A/PA/324A/PA/644A/PA/1284/P 10.12 Register description 10.12.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 10-2. Table 10-2.
PAGE 56
ATmega164A/PA/324A/PA/644A/PA/1284/P 10.12.2 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: 1. MCUCR Only available in the ATmega164PA/324PA/644PA/1284P. • Bit 6 – BODS: BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 10-1 on page 50.
PAGE 57
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 2 – PRSPI: Power Reduction Serial Peripheral Interface Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation. • Bit 1 – PRUSART0: Power Reduction USART0 Writing a logic one to this bit shuts down the USART0 by stopping the clock to the module.
PAGE 58
ATmega164A/PA/324A/PA/644A/PA/1284/P 11. System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
PAGE 59
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 11-1. Reset logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.1.2 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”” on page 333.
PAGE 60
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 11-3. MCU Start-up, RESET Extended Externally VCC VPOT RESET TIME-OUT VRST tTOUT INTERNAL RESET 11.1.3 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see ”” on page 333) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
PAGE 61
ATmega164A/PA/324A/PA/644A/PA/1284/P 11.1.4 Brown-out Detection ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
PAGE 62
ATmega164A/PA/324A/PA/644A/PA/1284/P 11.2 Internal Voltage Reference ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 11.2.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in ”” on page 333.
PAGE 63
ATmega164A/PA/324A/PA/644A/PA/1284/P 11.3 Watchdog Timer 11.3.1 Features • Clocked from separate On-chip Oscillator • Three operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 11.3.2 Overview ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator.
PAGE 64
ATmega164A/PA/324A/PA/644A/PA/1284/P 1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. The following code example shows one assembly and one C function for turning off the Watchdog Timer.
PAGE 65
ATmega164A/PA/324A/PA/644A/PA/1284/P always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization routine, even if the Watchdog is not in use. The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.
PAGE 66
ATmega164A/PA/324A/PA/644A/PA/1284/P 11.4 Register description 11.4.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset.
PAGE 67
ATmega164A/PA/324A/PA/644A/PA/1284/P 11.4.2 WDTCSR – Watchdog Timer Control Register Bit 7 6 5 4 3 2 1 0 (0x60) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCSR • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
PAGE 68
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 11-2 on page 68. Table 11-2. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT oscillator cycles Typical time-out at VCC = 5.
PAGE 69
ATmega164A/PA/324A/PA/644A/PA/1284/P 12. Interrupts 12.1 Overview This section describes the specifics of the interrupt handling as performed in ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. For a general explanation of the AVR interrupt handling, refer to ”Reset and interrupt handling” on page 24. 12.2 Interrupt Vectors in ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 12-1. Vector no.
PAGE 70
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 12-1. Vector no. Reset and Interrupt Vectors Program address (2) Source Interrupt definition 27 $0034 TWI two-wire Serial Interface 28 $0036 SPM_READY Store Program Memory Ready 29 $0038 USART1_RX USART1 Rx Complete 30 $003A USART1_UDRE USART1 Data Register Empty 31 $003C USART1_TX USART1 Tx Complete 32 $003E TIMER3_CAPT(3) 33 $0040 34 Notes: 2. 3. Timer/Counter3 Compare Match B TIMER3_COMPB $0044 1.
PAGE 71
ATmega164A/PA/324A/PA/644A/PA/1284/P The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is: Address Labels Code Comments 0x0000 jmp RESET ; Reset 0x0002 jmp INT0 ; IRQ0 0x0004 jmp INT1 ; IRQ1 0x0006 jmp INT2 ; IRQ2 0x0008 jmp PCINT0 ; PCINT0 0x000A jmp PCINT1 ; PCINT1 0x000C jmp PCINT2 ; PCINT2 0x000E jmp PCINT3 ; PCINT3 0x0010 jmp WDT ; Watchdog Timeout 0x0012 jmp TIM2_COMPA
PAGE 72
ATmega164A/PA/324A/PA/644A/PA/1284/P ; 0x0046 ldi r16,high(RAMEND) ; Main program start 0x0047 out SPH,r16 ; Set Stack Pointer to top of RAM 0x0048 ldi r16,low(RAMEND) 0x0049 out SPL,r16 0x004A sei 0x004B xxx ... ... ... Notes: RESET: ... ; Enable interrupts 1. Applies only to ATmega1284P.
PAGE 73
ATmega164A/PA/324A/PA/644A/PA/1284/P 0x1F003 0x1F004 0x1F005 outSPL,r16 sei; Enable interrupts xxx When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address ; .org 0x1F000 0x1F000 0x1F002 0x1F004 ...
PAGE 74
ATmega164A/PA/324A/PA/644A/PA/1284/P written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section.
PAGE 75
ATmega164A/PA/324A/PA/644A/PA/1284/P 13. External Interrupts 13.1 Overview The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as outputs. This feature provides a way of generating a software interrupt.
PAGE 76
ATmega164A/PA/324A/PA/644A/PA/1284/P defined in Table 13-1. Edges on INT2:INT0 are registered asynchronously. Pulses on INT2:0 pins wider than the minimum pulse width given in ”External interrupts characteristics” on page 334 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
PAGE 77
ATmega164A/PA/324A/PA/644A/PA/1284/P 13.2.4 PCICR – Pin Change Interrupt Control Register Bit 7 6 5 4 3 2 1 0 (0x68) – – – – PCIE3 PCIE2 PCIE1 PCIE0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCICR • Bit 3 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 3 is enabled. Any change on any enabled PCINT31:24 pin will cause an interrupt.
PAGE 78
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 1 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
PAGE 79
ATmega164A/PA/324A/PA/644A/PA/1284/P 13.2.9 PCMSK0 – Pin Change Mask Register 0 Bit 7 6 5 4 3 2 1 0 (0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK0 • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7..0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
PAGE 80
ATmega164A/PA/324A/PA/644A/PA/1284/P 14. I/O-Ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
PAGE 81
ATmega164A/PA/324A/PA/644A/PA/1284/P 14.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 14-2.
PAGE 82
ATmega164A/PA/324A/PA/644A/PA/1284/P 14.2.3 Switching between input and output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up.
PAGE 83
ATmega164A/PA/324A/PA/644A/PA/1284/P signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 144. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 14-4.
PAGE 84
ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example (1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
PAGE 85
ATmega164A/PA/324A/PA/644A/PA/1284/P 14.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode, and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
PAGE 86
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 14-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 14-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 14-2. Generic description of overriding signals for alternate functions Signal name Full name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
PAGE 87
ATmega164A/PA/324A/PA/644A/PA/1284/P 14.3.1 Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 14-3. Table 14-3.
PAGE 88
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 14-5.
PAGE 89
ATmega164A/PA/324A/PA/644A/PA/1284/P The alternate pin configuration is as follows: • SCK/OC3B/PCINT15 – Port B, Bit 7 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit.
PAGE 90
ATmega164A/PA/324A/PA/644A/PA/1284/P • AIN0/INT2/PCINT10, Bit 2 AIN0, Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. INT2, External Interrupt source 2. The PB2 pin can serve as an External Interrupt source to the MCU. PCINT10, Pin Change Interrupt source 10: The PB2 pin can serve as an external interrupt source. • T1/CLKO/PCINT9, Bit 1 T1, Timer/Counter1 counter source.
PAGE 91
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 14-8.
PAGE 92
ATmega164A/PA/324A/PA/644A/PA/1284/P • TOSC1/PCINT22 – Port C, Bit 6 TOSC1, Timer Oscillator pin 1. The PC6 pin can serve as an external interrupt source to the MCU. PCINT22, Pin Change Interrupt source 22: The PC6 pin can serve as an external interrupt source. • TDI/PCINT21 – Port C, Bit 5 TDI, JTAG Test Data Input. PCINT21, Pin Change Interrupt source 21: The PC5 pin can serve as an external interrupt source. • TDO/PCINT20 – Port C, Bit 4 TDO, JTAG Test Data Output.
PAGE 93
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 14-10.
PAGE 94
ATmega164A/PA/324A/PA/644A/PA/1284/P 14.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 14-12. Table 14-12.
PAGE 95
ATmega164A/PA/324A/PA/644A/PA/1284/P • OC1B/XCK1/PCINT28 – Port D, Bit 4 OC1B, Output Compare Match B output: The PB4 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDD4 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. XCK1, USART1 External clock. The Data Direction Register (DDB4) controls whether the clock is output (DDD4 set “one”) or input (DDD4 cleared).
PAGE 96
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 14-13.
PAGE 97
ATmega164A/PA/324A/PA/644A/PA/1284/P Register description 14.3.5 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: 1. MCUCR Only available in the ATmega164PA/324PA/644PA/1284P.
PAGE 98
ATmega164A/PA/324A/PA/644A/PA/1284/P 14.3.11 PINB – Port B Input Pins Address Bit 7 6 5 4 3 2 1 0 0x03 (0x23) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PINB 14.3.
PAGE 99
ATmega164A/PA/324A/PA/644A/PA/1284/P 15. 8-bit Timer/Counter0 with PWM 15.1 Features • • • • • • • 15.
PAGE 100
ATmega164A/PA/324A/PA/644A/PA/1284/P decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See Section “15.
PAGE 101
ATmega164A/PA/324A/PA/644A/PA/1284/P clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0).
PAGE 102
ATmega164A/PA/324A/PA/644A/PA/1284/P The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
PAGE 103
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 15-4. Compare Match Output unit, schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
PAGE 104
ATmega164A/PA/324A/PA/644A/PA/1284/P maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
PAGE 105
ATmega164A/PA/324A/PA/644A/PA/1284/P 15.7.3 Fast PWM mode The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7.
PAGE 106
ATmega164A/PA/324A/PA/644A/PA/1284/P The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.
PAGE 107
ATmega164A/PA/324A/PA/644A/PA/1284/P setting the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 15-4 on page 110). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
PAGE 108
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 15-9. Timer/Counter Timing diagram, with prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 15-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 15-10.
PAGE 109
ATmega164A/PA/324A/PA/644A/PA/1284/P 15.9 Register description 15.9.1 TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
PAGE 110
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 15-4. Compare Output mode, Phase Correct PWM mode (1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting. Note: 1.
PAGE 111
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 15-7 on page 111 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output mode, Phase Correct PWM mode (1) Table 15-7. COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: 1.
PAGE 112
ATmega164A/PA/324A/PA/644A/PA/1284/P 15.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
PAGE 113
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 15-9. Clock Select bit description (Continued) CS02 CS01 CS00 Description 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 15.9.
PAGE 114
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, that is, when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.
PAGE 115
ATmega164A/PA/324A/PA/644A/PA/1284/P 16. 16-bit Timer/Counter1 and Timer/Counter3(1) with PWM Note: 16.1 Timer/Counter3 is only available in ATmega1284/1284P Features • • • • • • • • • • • 16.2 1.
PAGE 116
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-1. 16-bit Timer/Counter block diagram (1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 1.
PAGE 117
ATmega164A/PA/324A/PA/644A/PA/1284/P The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See Section “22.” on page 240) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
PAGE 118
ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Examples (1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples (1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. The example code assumes that the part specific header file is included.
PAGE 119
ATmega164A/PA/324A/PA/644A/PA/1284/P The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
PAGE 120
ATmega164A/PA/324A/PA/644A/PA/1284/P The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
PAGE 121
ATmega164A/PA/324A/PA/644A/PA/1284/P The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling.
PAGE 122
ATmega164A/PA/324A/PA/644A/PA/1284/P The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 16.7 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a timestamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit.
PAGE 123
ATmega164A/PA/324A/PA/644A/PA/1284/P 16.7.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICPn). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture.
PAGE 124
ATmega164A/PA/324A/PA/644A/PA/1284/P Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 127). A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 16-4 shows a block diagram of the Output Compare unit.
PAGE 125
ATmega164A/PA/324A/PA/644A/PA/1284/P 16.8.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or toggled). 16.8.
PAGE 126
ATmega164A/PA/324A/PA/644A/PA/1284/P Compare Match Output unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 16-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
PAGE 127
ATmega164A/PA/324A/PA/644A/PA/1284/P 16.9.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 16-2 on page 136.
PAGE 128
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-6. CTC mode, timing diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
PAGE 129
ATmega164A/PA/324A/PA/644A/PA/1284/P In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 16-7. The figure shows fast PWM mode when OCRnA or ICRn is used to define TOP.
PAGE 130
ATmega164A/PA/324A/PA/644A/PA/1284/P pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
PAGE 131
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-8. Phase Correct PWM mode, timing diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM.
PAGE 132
ATmega164A/PA/324A/PA/644A/PA/1284/P The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
PAGE 133
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-9. Phase and Frequency Correct PWM mode, timing diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
PAGE 134
ATmega164A/PA/324A/PA/644A/PA/1284/P output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 16.11 Timer/Counter Timing diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures.
PAGE 135
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-12. Timer/Counter Timing diagram, no prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) New OCRnx Value Old OCRnx Value Figure 16-13 shows the same timing data, but with the prescaler enabled. Figure 16-13.
PAGE 136
ATmega164A/PA/324A/PA/644A/PA/1284/P 16.12 Register description 16.12.1 TCCRnA – Timer/Counter n Control Register A Bit 7 6 5 4 3 2 1 0 COMnA1 COMnA0 COMnB1 COMnB0 – – WGMn1 WGMn0 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x80) TCCRnA • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respectively) behavior.
PAGE 137
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 16-4 on page 137 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Compare Output mode, phase correct and phase and frequency correct PWM (1) Table 16-4. COMnA1/COMnB1 COMnA0/COMnB0 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 WGMn3:0 = 9 or 11: Toggle OCnA on Compare Match, OCnB disconnected (normal port operation).
PAGE 138
ATmega164A/PA/324A/PA/644A/PA/1284/P Waveform Generation mode bit description (1) Table 16-5.
PAGE 139
ATmega164A/PA/324A/PA/644A/PA/1284/P When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written.
PAGE 140
ATmega164A/PA/324A/PA/644A/PA/1284/P 16.12.4 TCNT1H and TCNT1L –Timer/Counter1 Bit 7 6 5 4 3 (0x85) TCNT1[15:8] (0x84) TCNT1[7:0] 2 1 0 TCNT1H TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter.
PAGE 141
ATmega164A/PA/324A/PA/644A/PA/1284/P The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 117. 16.12.
PAGE 142
ATmega164A/PA/324A/PA/644A/PA/1284/P The Input Capture is updated with the counter (TCNT3) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter3). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP).
PAGE 143
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 5 – ICIE3: Timer/Counter3, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 69) is executed when the ICF3 Flag, located in TIFR3, is set. • Bit 4:3 – Reserved These bits are unused and will always read as zero.
PAGE 144
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
PAGE 145
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 0 – TOV3: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOV3 Flag is set when the timer overflows. Refer to Table 16-5 on page 138 for the TOV3 Flag behavior when using another WGMn3:0 bit setting. TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt Vector is executed. Alternatively, TOV3 can be cleared by writing a logic one to its bit location.
PAGE 146
ATmega164A/PA/324A/PA/644A/PA/1284/P 17. 8-bit Timer/Counter2 with PWM and asynchronous operation 17.1 Features • • • • • • • Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 16-12.. For the actual placement of I/O pins, see ”Pin configurations” on page 11. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold.
PAGE 147
ATmega164A/PA/324A/PA/644A/PA/1284/P 17.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
PAGE 148
ATmega164A/PA/324A/PA/644A/PA/1284/P 17.4 Counter unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 17-2 shows a block diagram of the counter and its surrounding environment. Figure 17-2. Counter Unit block diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1.
PAGE 149
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 17-3. Output Compare unit, block diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
PAGE 150
ATmega164A/PA/324A/PA/644A/PA/1284/P Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the COM2x1:0 bits will take effect immediately. 17.6 Compare Match Output unit The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match. Also, the COM2x1:0 bits control the OC2x pin output source.
PAGE 151
ATmega164A/PA/324A/PA/644A/PA/1284/P 17.7 Modes of operation The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or noninverted PWM).
PAGE 152
ATmega164A/PA/324A/PA/644A/PA/1284/P For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00).
PAGE 153
ATmega164A/PA/324A/PA/644A/PA/1284/P In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when WGM2:0 = 7 (See Table 17-3 on page 159). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output.
PAGE 154
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 17-7. Phase Correct PWM mode, timing diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin.
PAGE 155
ATmega164A/PA/324A/PA/644A/PA/1284/P 17.8 Timer/Counter Timing diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 17-8 on page 155 contains timing data for basic Timer/Counter operation.
PAGE 156
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 17-10. Timer/Counter Timing diagram, setting of OCF2A, with prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 17-11 on page 156 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 17-11.
PAGE 157
ATmega164A/PA/324A/PA/644A/PA/1284/P registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2x write in progress.
PAGE 158
ATmega164A/PA/324A/PA/644A/PA/1284/P 17.10 Timer/Counter Prescaler Figure 17-12. Prescaler for Timer/Counter2 PSRASY clkT2S/1024 clkT2S/256 clkT2S/128 AS2 clkT2S/64 10-BIT T/C PRESCALER Clear clkT2S/32 TOSC1 clkT2S clkT2S/8 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
PAGE 159
ATmega164A/PA/324A/PA/644A/PA/1284/P 17.11 Register description 17.11.1 TCCR2A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior.
PAGE 160
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 17-4. Compare Output mode, phase correct PWM mode (1) COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Match when down-counting. 1 1 Set OC2A on Compare Match when up-counting. Clear OC2A on Compare Match when down-counting. Note: 1.
PAGE 161
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 17-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Compare Output mode, phase correct PWM mode (1) Table 17-7. COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on Compare Match when up-counting. Set OC2B on Compare Match when down-counting. 1 1 Set OC2B on Compare Match when up-counting. Clear OC2B on Compare Match when down-counting. Note: 1.
PAGE 162
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is changed according to its COM2A1:0 bits setting.
PAGE 163
ATmega164A/PA/324A/PA/644A/PA/1284/P The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers. 17.11.
PAGE 164
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 2 – OCR2BUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.
PAGE 165
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 2 – OCF2B: Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag.
PAGE 166
ATmega164A/PA/324A/PA/644A/PA/1284/P 18. SPI – Serial Peripheral Interface 18.1 Features • • • • • • • • Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P and peripheral devices or between several AVR devices. USART can also be used in Master SPI mode, see ”USART in SPI mode” on page 202.
PAGE 167
ATmega164A/PA/324A/PA/644A/PA/1284/P The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
PAGE 168
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 18-1. Pin SPI pin overrides (1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See ”Alternate Functions of Port B” on page 88 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
PAGE 169
ATmega164A/PA/324A/PA/644A/PA/1284/P Note: 1. See “About code examples” on page 17. The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
PAGE 170
ATmega164A/PA/324A/PA/644A/PA/1284/P 18.3 SS pin functionality 18.3.1 Slave mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
PAGE 171
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 18-2. SPI modes SPI Mode Conditions Leading Edge Trailing Edge 0 CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 1 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 2 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 3 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) Figure 18-3.
PAGE 172
ATmega164A/PA/324A/PA/644A/PA/1284/P 18.5 Register description 18.5.1 SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
PAGE 173
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bits 1:0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 18-5.
PAGE 174
ATmega164A/PA/324A/PA/644A/PA/1284/P 18.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.  2018 Microchip Technology Inc.
PAGE 175
ATmega164A/PA/324A/PA/644A/PA/1284/P 19. USART 19.1 Features • • • • • • • • • • • • 19.
PAGE 176
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 19-1. USART block diagram (1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1.
PAGE 177
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 19-2. Clock Generation Logic, block diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector 0 UCPOL txclk UMSEL 1 xcko DDR_XCK 1 1 0 rxclk Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
PAGE 178
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 19-1.
PAGE 179
ATmega164A/PA/324A/PA/644A/PA/1284/P used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCKn clock frequency is limited by the following equation: f OSC f XCK  ----------4 Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 19.4.
PAGE 180
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 19-4. Frame formats FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) StStart bit, always low. (n)Data bits (0 to 8). PParity bit. Can be odd or even. SpStop bit, always high. IDLENo transfers on the communication line (RxDn or TxDn). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting.
PAGE 181
ATmega164A/PA/324A/PA/644A/PA/1284/P frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers.
PAGE 182
ATmega164A/PA/324A/PA/644A/PA/1284/P are ignored. The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R16.
PAGE 183
ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example (1)(2) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Copy 9th bit from r17 to TXB8 cbi UCSRnB,TXB8 sbrc r17,0 sbi UCSRnB,TXB8 ; Put LSB data (r16) into buffer, sends the data out UDRn,r16 ret C Code Example (1)(2) void USART_Transmit( unsigned int data ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
PAGE 184
ATmega164A/PA/324A/PA/644A/PA/1284/P transmitting application must enter receive mode and free the communication bus immediately after completing the transmission. When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that global interrupts are enabled).
PAGE 185
ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example (1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret C Code Example (1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<
PAGE 186
ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example (1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
PAGE 187
ATmega164A/PA/324A/PA/644A/PA/1284/P 19.8.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data).
PAGE 188
ATmega164A/PA/324A/PA/644A/PA/1284/P 19.8.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost 19.8.
PAGE 189
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 19-5. Start bit sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
PAGE 190
ATmega164A/PA/324A/PA/644A/PA/1284/P The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 19-7 on page 189.
PAGE 191
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 19-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow [%] Rfast [%] Maximum total error [%] Recommended max. receiver error [%] 5 93.20 106.67 +6.67/-6.8 ±3.0 6 94.12 105.79 +5.79/-5.88 ±2.5 7 94.81 105.11 +5.11/-5.19 ±2.0 8 95.36 104.58 +4.58/-4.54 ±2.0 9 95.81 104.14 +4.14/-4.19 ±1.5 10 96.17 103.78 +3.78/-3.83 ±1.5 Table 19-3.
PAGE 192
ATmega164A/PA/324A/PA/644A/PA/1284/P 19.10.1 Using MPCMn For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame (TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character frame format. The following procedure should be used to exchange data in Multi-processor Communication mode: 1.
PAGE 193
ATmega164A/PA/324A/PA/644A/PA/1284/P 19.11 Register description 19.11.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
PAGE 194
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. • Bit 3 – DORn: Data OverRun This bit is set if a Data OverRun condition is detected.
PAGE 195
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn Flags. • Bit 3 – TXENn: Transmitter Enable n Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxDn pin when enabled.
PAGE 196
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 19-5. UPMn bits settings UPMn1 UPMn0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 19-6.
PAGE 197
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 19-8. UCPOLn bit settings Transmitted data changed (output of TxDn pin) Received data sampled (input on RxDn pin) 0 Rising XCKn Edge Falling XCKn Edge 1 Falling XCKn Edge Rising XCKn Edge UCPOLn 19.11.
PAGE 198
ATmega164A/PA/324A/PA/644A/PA/1284/P 19.12 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 19-9 to Table 19-12. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
PAGE 199
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 19-10. Examples of UBRRn settings for commonly used oscillator frequencies. (Continued) fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud rate [bps] UBRR 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.
PAGE 200
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 19-11. Examples of UBRRn settings for commonly used oscillator frequencies (Continued) fosc = 8.0000MHz fosc = 11.0592MHz fosc = 14.7456MHz Baud rate [bps] UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.
PAGE 201
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 19-12. Examples of UBRRn settings for commonly used oscillator frequencies (Continued) fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz Baud rate [bps] UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.
PAGE 202
ATmega164A/PA/324A/PA/644A/PA/1284/P 20. USART in SPI mode 20.1 Features • • • • • • • • 20.
PAGE 203
ATmega164A/PA/324A/PA/644A/PA/1284/P 20.4 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 20-1. Data bits are shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn functionality is summarized in Table 20-2.
PAGE 204
ATmega164A/PA/324A/PA/644A/PA/1284/P independently. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and thus interrupts globally disabled) when doing the initialization. Note: To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be zero at the time the transmitter is enabled.
PAGE 205
ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example (1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<
PAGE 206
ATmega164A/PA/324A/PA/644A/PA/1284/P clock. The data written to UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame. Note: To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must be read once for each byte transmitted. The input buffer operation is identical to normal USART mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the buffer.
PAGE 207
ATmega164A/PA/324A/PA/644A/PA/1284/P 20.6.2 Disabling the Transmitter or Receiver The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation. 20.7 AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding:  Master mode timing diagram.
PAGE 208
ATmega164A/PA/324A/PA/644A/PA/1284/P 20.8 Register description The following section describes the registers used for SPI operation using the USART. 20.8.1 UDRn – USART MSPIM I/O Data Register The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation. See “UDRn – USART I/O Data Register n” on page 193. 20.8.
PAGE 209
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 6 – TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. • Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag.
PAGE 210
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 5:3 – Reserved in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnC is written. • Bit 2 – UDORDn: Data Order When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to ”Frame Formats” on page 203 for details.
PAGE 211
ATmega164A/PA/324A/PA/644A/PA/1284/P 21. Two-wire Serial Interface 21.1 Features • • • • • • • • • • 21.
PAGE 212
ATmega164A/PA/324A/PA/644A/PA/1284/P The Power Reduction TWI bit, PRTWI bit in ”PRR0 – Power Reduction Register 0” on page 56 must be written to zero to enable the two-wire Serial Interface. 21.2.2 Electrical Interconnection As depicted in Figure 21-1, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface.
PAGE 213
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-3. START, REPEATED START and STOP conditions SDA SCL START STOP REPEATED START START STOP 21.3.3 Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
PAGE 214
ATmega164A/PA/324A/PA/644A/PA/1284/P should inform the Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 21-5. Data packet format Data MSB Data LSB ACK 8 9 Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 2 SLA+R/W 7 STOP, REPEATED START or Next Data Byte Data Byte 21.3.
PAGE 215
ATmega164A/PA/324A/PA/644A/PA/1284/P arbitration process, it should immediately switch to Slave mode to check whether it is being addressed by the winning master. The fact that multiple masters have started transmission at the same time should not be detectable to the slaves, that is the data being transferred on the bus must not be corrupted  Different masters may use different SCL frequencies.
PAGE 216
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-8. Arbitration between two masters START Master A Loses Arbitration, SDAA SDA SDA from Master A SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between:  A REPEATED START condition and a data bit  A STOP condition and a data bit  A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
PAGE 217
ATmega164A/PA/324A/PA/644A/PA/1284/P 21.5 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 21-9. All registers drawn in a thick line are accessible through the AVR data bus.
PAGE 218
ATmega164A/PA/324A/PA/644A/PA/1284/P CPU Clock frequency SCL frequency = ----------------------------------------------------------TWPS 16 + 2(TWBR)  4  TWBR = Value of the TWI Bit Rate Register  TWPS = Value of the prescaler bits in the TWI Status Register Note: Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See two-wire Serial Bus Requirements in Table 28-16 on page 336 for value of pull-up resistor. 21.5.
PAGE 219
ATmega164A/PA/324A/PA/644A/PA/1284/P Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer.
PAGE 220
ATmega164A/PA/324A/PA/644A/PA/1284/P 4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the address packet has successfully been sent. The status code will also reflect whether a Slave acknowledged the packet or not. 5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected.
PAGE 221
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 21-2. Assembly code and C code examples Assembly code example 1 2 3 4 ldi r16, (1<
PAGE 222
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 21-2. Assembly code and C code examples Assembly code example 5 6 7 in r16,TWSR andi r16, 0xF8 cpi r16, MT_SLA_ACK brne ERROR ldi r16, DATA out TWDR, r16 ldi r16, (1<
PAGE 223
ATmega164A/PA/324A/PA/644A/PA/1284/P R:Read bit (high level at SDA) W:Write bit (low level at SDA) A:Acknowledge bit (low level at SDA) A:Not acknowledge bit (high level at SDA) Data: 8-bit data byte P:STOP condition SLA:Slave Address In Figure 21-12 on page 225 to Figure 21-18 on page 233, circles are used to indicate that the TWINT Flag is set. The numbers in the circles show the status code held in TWSR, with the prescaler bits masked to zero.
PAGE 224
ATmega164A/PA/324A/PA/644A/PA/1284/P When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes is detailed in Table 21-3 on page 224. When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing the data byte to TWDR.
PAGE 225
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 21-3.
PAGE 226
ATmega164A/PA/324A/PA/644A/PA/1284/P 21.7.2 Master Receiver mode In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter (Slave see Figure 21-13 on page 226). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
PAGE 227
ATmega164A/PA/324A/PA/644A/PA/1284/P After a repeated START condition (state 0x10) the two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 21-4.
PAGE 228
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-14.
PAGE 229
ATmega164A/PA/324A/PA/644A/PA/1284/P The upper seven bits are the address to which the two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI.
PAGE 230
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 21-5.
PAGE 231
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-16. Formats and states in the Slave Receiver mode Reception of the own slave address and one or more data bytes.
PAGE 232
ATmega164A/PA/324A/PA/644A/PA/1284/P To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
PAGE 233
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 21-6.
PAGE 234
ATmega164A/PA/324A/PA/644A/PA/1284/P writing a logic one to it. This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted. Table 21-7.
PAGE 235
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-20. An Arbitration example VCC Device 1 Device 2 Device 3 MASTER TRANSMITTER MASTER TRANSMITTER SLAVE RECEIVER ........ Device n R1 R2 SDA SCL Several different scenarios may arise during arbitration, as described below:  Two or more masters are performing identical communication with the same Slave.
PAGE 236
ATmega164A/PA/324A/PA/644A/PA/1284/P 21.9 Register description 21.9.1 TWBR – TWI Bit Rate Register Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB8) TWBR • Bits 7:0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
PAGE 237
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition.
PAGE 238
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 21-8. TWI Bit Rate Prescaler TWPS1 TWPS0 Prescaler value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, see ”Bit Rate Generator unit” on page 217. The value of TWPS1..0 is used in the equation. 21.9.
PAGE 239
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the two-wire Serial Bus. 21.9.6 TWAMR – TWI (Slave) Address Mask Register Bit 7 6 5 (0xBD) 4 3 2 1 0 – TWAM[6:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TWAMR • Bits 7:1 – TWAM: TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask.
PAGE 240
ATmega164A/PA/324A/PA/644A/PA/1284/P 22. AC - Analog Comparator 22.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
PAGE 241
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 22-1. 22.3 Analog Comparator Mulitiplexed input (Continued) ACME ADEN MUX2..0 Analog Comparator negative input 1 0 011 ADC3 1 0 100 ADC4 1 0 101 ADC5 1 0 110 ADC6 1 0 111 ADC7 Register description 22.3.
PAGE 242
ATmega164A/PA/324A/PA/644A/PA/1284/P ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
PAGE 243
ATmega164A/PA/324A/PA/644A/PA/1284/P 23. ADC - Analog-to-digital converter 23.1 Features • • • • • • • • • • • • • • • 10-bit resolution 0.5LSB integral non-linearity ±2LSB absolute accuracy 13 - 260µs conversion time Up to 15kSPS at maximum resolution Eight multiplexed single ended input channels Differential mode with selectable gain at 1×, 10×, or 200× Optional left adjustment for ADC result readout 0 - VCC ADC input voltage range 2.7 - VCC differential ADC voltage range Selectable 2.56V or 1.
PAGE 244
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 23-1. Analog-to-digital Converter block schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] AREF ADSC ADATE ADC[9:0] ADIF ADPS[2:0] ADEN DIFF / GAIN SELECT CHANNEL SELECTION INTERNAL REFERENCE (1.1V/2.
PAGE 245
ATmega164A/PA/324A/PA/644A/PA/1284/P The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL.
PAGE 246
ATmega164A/PA/324A/PA/644A/PA/1284/P this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. Prescaling and Conversion Timing Figure 23-3.
PAGE 247
ATmega164A/PA/324A/PA/644A/PA/1284/P In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 23-1 on page 248. Figure 23-4.
PAGE 248
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 23-7. ADC Timing diagram, free running conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 3 2 4 ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete Table 23-1. MUX and REFS Update ADC conversion time Condition Sample & Hold (cycles from start of conversion) Conversion time (cycles) First conversion 14.5 25 Normal conversions, single ended 1.5 13 2 13.5 1.5/2.
PAGE 249
ATmega164A/PA/324A/PA/644A/PA/1284/P 23.6 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started.
PAGE 250
ATmega164A/PA/324A/PA/644A/PA/1284/P AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant voltmeter.
PAGE 251
ATmega164A/PA/324A/PA/644A/PA/1284/P Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 23-8. Analog input circuitry IIH ADCn 1..100 kΩ CS/H= 14 pF IIL VCC/2 23.7.
PAGE 252
ATmega164A/PA/324A/PA/644A/PA/1284/P Analog Ground Plane PA3 (ADC3) PA2 (ADC2) PA1 (ADC1) PA0 (ADC0) VCC ADC Power Connections GND Figure 23-9. PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) GND AVCC 100nF AREF 10μH PA7 (ADC7) PC7 23.7.3 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible.
PAGE 253
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 23-10. Offset error Output Code Ideal ADC Actual ADC Offset Error  VREF Input Voltage Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5LSB below maximum). Ideal value: 0LSB Figure 23-11.
PAGE 254
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 23-12. Integral non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF  Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1LSB). Ideal value: 0LSB Figure 23-13.
PAGE 255
ATmega164A/PA/324A/PA/644A/PA/1284/P 23.8 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN  1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 23-3 on page 257 and Table 23-4 on page 257).
PAGE 256
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 23-2. Correlation between input voltage and output codes VADCn Read code Corresponding decimal value VADCm + VREF/GAIN 0x1FF 511 VADCm + 0.999VREF/GAIN 0x1FF 511 VADCm + 0.998VREF/GAIN 0x1FE 510 ... ... ... VADCm + 0.001VREF/GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001VREF/GAIN 0x3FF -1 ... ... ... VADCm - 0.999VREF/GAIN 0x201 -511 VADCm - VREF/GAIN 0x200 -512 Example: ADMUX = 0xED (ADC3 - ADC2, 10× gain, 2.
PAGE 257
ATmega164A/PA/324A/PA/644A/PA/1284/P 23.9 Register description 23.9.1 ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7C) ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 23-3.
PAGE 258
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 23-4. MUX4..
PAGE 259
ATmega164A/PA/324A/PA/644A/PA/1284/P enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. • Bit 5 – ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled.
PAGE 260
ATmega164A/PA/324A/PA/644A/PA/1284/P ADLA R = 1 Bit 15 14 13 12 11 10 9 8 (0x79) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH (0x78) ADC1 ADC0 – – – – – – ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form.
PAGE 261
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 7, 5:3 – Reserved These bits are reserved for future use in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. For ensuring compatibility with future devices, these bits must be written zero when ADCSRB is written. • Bit 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect.
PAGE 262
ATmega164A/PA/324A/PA/644A/PA/1284/P 24. JTAG interface and on-chip debug system 24.1 Features • JTAG (IEEE std. 1149.1 Compliant) interface • Boundary-scan capabilities according to the IEEE std. 1149.
PAGE 263
ATmega164A/PA/324A/PA/644A/PA/1284/P  TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains)  TDO: Test Data Out. Serial output data from Instruction Register or Data Register The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the TAP controller is in reset.
PAGE 264
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 24-2. TAP controller state diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 24.
PAGE 265
ATmega164A/PA/324A/PA/644A/PA/1284/P  At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during input of all bits except the MSB.
PAGE 266
ATmega164A/PA/324A/PA/644A/PA/1284/P The Atmel Studio enables the user to fully control execution of programs on an AVR device with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator. Atmel Studio supports source level execution of Assembly programs assembled with AVR Assembler and C programs compiled with third party vendors’ compilers. Atmel Studio runs under Microsoft® Windows® 95/98/2000 and Microsoft Windows NT®.
PAGE 267
ATmega164A/PA/324A/PA/644A/PA/1284/P 24.9 Bibliography For more information about general Boundary-scan, the following literature can be consulted:  IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993  Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992 24.10 Register description 24.10.
PAGE 268
ATmega164A/PA/324A/PA/644A/PA/1284/P 25. IEEE 1149.1 (JTAG) Boundary-scan 25.1 Features • • • • • 25.2 JTAG (IEEE std. 1149.
PAGE 269
ATmega164A/PA/324A/PA/644A/PA/1284/P 25.3 Data Registers The Data Registers relevant for Boundary-scan operations are:  Bypass Register  Device Identification Register  Reset Register  Boundary-scan Chain 25.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state.
PAGE 270
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 25-2. Reset register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 25.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See ”Boundary-scan Chain” on page 271 for a complete description. 25.
PAGE 271
ATmega164A/PA/324A/PA/644A/PA/1284/P 25.4.2 IDCODE; 0x1 Optional JTAG instruction selecting the 32-bit ID-Register as Data Register. The ID-Register consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after power-up. The active states are:  Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain  Shift-DR: The IDCODE scan chain is shifted by the TCK input 25.4.
PAGE 272
ATmega164A/PA/324A/PA/644A/PA/1284/P The Boundary-scan logic is not included in the figures in the datasheet. Figure 25-4 shows a simple digital port pin as described in the section ”I/O-Ports” on page 80. The Boundary-scan details from Figure 25-3 replaces the dashed box in Figure 25-4 on page 273.
PAGE 273
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 25-4.
PAGE 274
ATmega164A/PA/324A/PA/644A/PA/1284/P 25.6 ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Boundary-scan order Table 25-1 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A and Port K is scanned in the opposite bit order of the other ports.
PAGE 275
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 25-1. 25.7 ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Boundary-scan order Bit number Signal name 27 PD6.Data 26 PD6.Control 25 PD7.Data 24 PD7.Control 23 PC0.Data 22 PC0.Control 21 PC1.Data 20 PC1.Control 19 PC6.Data 18 PC6.Control 17 PC7.Data 16 PC7.Control 15 PA7.Data 14 PA7.Control 13 PA6.Data 12 PA6.Control 11 PA5.Data 10 PA5.Control 9 PA4.Data 8 PA4.Control 7 PA3.Data 6 PA3.Control 5 PA2.Data 4 PA2.
PAGE 276
ATmega164A/PA/324A/PA/644A/PA/1284/P 25.8 Register description 25.8.1 MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: 1. MCUCR Only available in the ATmega164PA/324PA/644PA/1284P.
PAGE 277
ATmega164A/PA/324A/PA/644A/PA/1284/P 26. Boot loader support – read-while-write self-programming 26.1 Features • • • • • • • Read-while-write self-programming Flexible boot memory size High security (separate Boot Lock bits for a flexible protection) Separate fuse to select reset vector Optimized page (1) size Code efficient algorithm Efficient read-modify-write support Note: 26.2 1. A page is a section in the Flash consisting of several bytes (see Table 27-7 on page 298) used during programming.
PAGE 278
ATmega164A/PA/324A/PA/644A/PA/1284/P 26.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-Write (NRWW) section.
PAGE 279
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 26-1. Read-While-Write vs. No Read-While-Write Read-While-Write (RWW) Section Z-pointer Addresses RWW Section Z-pointer Addresses NRWW Section No Read-While-Write (NRWW) Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation  2018 Microchip Technology Inc.
PAGE 280
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 26-2.
PAGE 281
ATmega164A/PA/324A/PA/644A/PA/1284/P Boot Lock Bit0 protection modes (application section) (1) Table 26-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or (E)LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and (E)LPM executing from the Boot Loader section is not allowed to read from the Application section.
PAGE 282
ATmega164A/PA/324A/PA/644A/PA/1284/P 26.7 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers ZL and ZH in the register file, and RAMPZ in the I/O space. The number of bits actually used is implementation dependent. Note that the RAMPZ register is only implemented when the program space is larger than 64K bytes.
PAGE 283
ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
PAGE 284
ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.4 Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading.
PAGE 285
ATmega164A/PA/324A/PA/644A/PA/1284/P within four CPU cycles. When BLBSET and SPMEN are cleared, (E)LPM will work as described in the Instruction set Manual. Bit 7 6 5 4 3 2 1 0 Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1 The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR.
PAGE 286
ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.11 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low.
PAGE 287
ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.13 Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
PAGE 288
ATmega164A/PA/324A/PA/644A/PA/1284/P ldi PAGESIZEB<=256 subi sbci Rdloop: lpm ld cpse jmp sbiw PAGESIZEB<=256 brne loophi, high(PAGESIZEB) ;not required for YL, low(PAGESIZEB) YH, high(PAGESIZEB) ;restore pointer r0, Z+ r1, Y+ r0, r1 Error loophi:looplo, 1 ;use subi for Rdloop ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
PAGE 289
ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.14 ATmega164A/ATmega164PA Boot Loader Parameters In Table 26-7 through Table 26-9, the parameters used in the description of the Self-Programming are given. Table 26-7.
PAGE 290
ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.15 ATmega324A/ATmega324PA Boot Loader Parameters In Table 26-10 through Table 26-12, the parameters used in the description of the Self-Programming are given. Table 26-10.
PAGE 291
ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.16 ATmega644A/ATmega644PA Boot Loader parameters In Table 26-13 through Table 26-15, the parameters used in the description of the Self-Programming are given. Table 26-13.
PAGE 292
ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.17 ATmega1284/ATmega1284P Boot Loader parameters In Table 26-16 through Table 26-18, the parameters used in the description of the Self-Programming are given. Table 26-16.
PAGE 293
ATmega164A/PA/324A/PA/644A/PA/1284/P 26.9 Register description 26.9.1 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
PAGE 294
ATmega164A/PA/324A/PA/644A/PA/1284/P Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. • Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored.
PAGE 295
ATmega164A/PA/324A/PA/644A/PA/1284/P 27. Memory programming 27.1 Program And Data Memory Lock Bits The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 27-2. The Lock bits can only be erased to “1” with the Chip Erase command. Lock Bit byte (1) Table 27-1.
PAGE 296
ATmega164A/PA/324A/PA/644A/PA/1284/P Lock Bit protection modes (1)(2) (Continued) Table 27-2. Memory Lock bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or (E)LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from the Application section is not allowed to read from the Boot Loader section.
PAGE 297
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-4. Fuse High byte Fuse High byte Bit no. Description Default value OCDEN (4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN (1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
PAGE 298
ATmega164A/PA/324A/PA/644A/PA/1284/P 27.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 27.3 Signature Bytes All AVR microcontrollers have a three-byte signature code which identifies the device.
PAGE 299
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-8. Number of words in a page and number of pages in the EEPROM Device EEPROM size Page size PCWORD No. of pages PCPAGE EEAMSB ATmega164A/ATmega164PA 512bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8 ATmega324A/ATmega324PA 1KBytes 4 bytes EEA[1:0] 256 EEA[9:2] 9 ATmega644A/ATmega644PA 2KBytes 8 bytes EEA[2:0] 256 EEA[10:2] 10 ATmega1284/ATmega1284P 4KBytes 8 bytes EEA[2:0] 512 EEA[11:3] 11 27.
PAGE 300
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-9. Pin name mapping Signal name in programming mode Pin name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command OE PD2 I Output Enable (Active low). WR PD3 I Write Pulse (Active low). BS1 PD4 I Byte Select 1. XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 PAGEL PD7 I Program Memory and EEPROM data Page Load. BS2 PA0 I Byte Select 2. DATA PB7-0 I/O Table 27-10.
PAGE 301
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-13. Command byte bit encoding Command byte 27.7 Command executed 1000 0000 Chip Erase 0100 0000 Write Fuse bits 0010 0000 Write Lock bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM Parallel programming 27.7.1 Enter Programming mode The following algorithm puts the device in parallel programming mode: 1.
PAGE 302
ATmega164A/PA/324A/PA/644A/PA/1284/P 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. 27.7.4 Programming the Flash The Flash is organized in pages, see Table 27-7 on page 298. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously.
PAGE 303
ATmega164A/PA/324A/PA/644A/PA/1284/P 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS2, BS1 to “10”. This selects the address extended high byte. 3. Set DATA = Address extended high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. I. Program Page 1. Set BS2, BS1 to “00”. 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 3.
PAGE 304
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-3. Programming the flash waveforms (1). F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G H ADDR. HIGH ADDR. EXT.H I XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL Note: 1. “XX” is don’t care. The letters refer to the programming description above. 27.7.5 Programming the EEPROM The EEPROM is organized in pages, see Table 27-8 on page 299.
PAGE 305
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-4. Programming the EEPROM waveforms. K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C E DATA XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 27.7.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to ”Programming the Flash” on page 302 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. H: Load Address Extended Byte (0x00- 0xFF). 3.
PAGE 306
ATmega164A/PA/324A/PA/644A/PA/1284/P 27.7.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to ”Programming the Flash” on page 302 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS2, BS1 to “01”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS2, BS1 to “00”.
PAGE 307
ATmega164A/PA/324A/PA/644A/PA/1284/P 27.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to ”Programming the Flash” on page 302 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4.
PAGE 308
ATmega164A/PA/324A/PA/644A/PA/1284/P 27.7.15 Parallel Programming Characteristics Table 27-14. Parallel programming characteristics, VCC = 5V ±10% Symbol Parameter Min. VPP Programming Enable Voltage 11.
PAGE 309
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-7. Parallel programming timing, including some general timing requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 27-8.
PAGE 310
ATmega164A/PA/324A/PA/644A/PA/1284/P operations can be executed. NOTE, in Table 27-15, the pin mapping for serial programming is listed. Not all packages use the SPI pins dedicated for the internal Serial Peripheral Interface - SPI. 27.8.1 Serial Programming Pin Mapping Table 27-15. Pin mapping serial programming Symbol Pins (PDIP-40) Pins (TQFP/MLF-44) I/O Description MOSI PB5 PB5 I Serial Data in MISO PB6 PB6 O Serial Data out SCK PB7 PB7 I Serial Clock Figure 27-10.
PAGE 311
ATmega164A/PA/324A/PA/644A/PA/1284/P 2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted.
PAGE 312
ATmega164A/PA/324A/PA/644A/PA/1284/P 27.9 Serial Programming Instruction set Table 27-17 and Figure 27-11 on page 313 describes the Instruction set. Table 27-17.
PAGE 313
ATmega164A/PA/324A/PA/644A/PA/1284/P Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 27-11. Figure 27-11.
PAGE 314
ATmega164A/PA/324A/PA/644A/PA/1284/P 27.9.1 Serial Programming Characteristics For characteristics of the Serial Programming module see “SPI timing characteristics” on page 335. Figure 27-12. Serial programming waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE 27.10 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO.
PAGE 315
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-13. State machine sequence for changing the instruction word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 1 Exit1-IR 0 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 27.10.
PAGE 316
ATmega164A/PA/324A/PA/644A/PA/1284/P  Capture-DR: The result of the previous command is loaded into the Data Register  Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command  Update-DR: The programming command is applied to the Flash inputs  Run-Test/Idle: One clock cycle is generated, executing the applied command 27.10.
PAGE 317
ATmega164A/PA/324A/PA/644A/PA/1284/P Register. The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 25-2 on page 270. 27.10.9 Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled.
PAGE 318
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-18. JTAG programming instruction. Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence 0100011_10000000 xxxxxxx_xxxxxxxx 0110001_10000000 xxxxxxx_xxxxxxxx 0110011_10000000 xxxxxxx_xxxxxxxx 0110011_10000000 xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
PAGE 319
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-18. JTAG programming instruction. (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 4g.
PAGE 320
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-18. JTAG programming instruction. (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence 8a.
PAGE 321
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-16. State machine sequence for changing/reading the data word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 1 Exit1-IR 0 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 1 1 0 1 Update-IR 0 1 0 27.10.
PAGE 322
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-17. Flash data byte register STROBES TDI State Machine ADDRESS Flash EEPROM Fuses Lock Bits D A T A TDO The state machine controlling the Flash Data Byte Register is clocked by TCK.
PAGE 323
ATmega164A/PA/324A/PA/644A/PA/1284/P 27.10.16Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 322. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address Extended High byte using programming instruction 2b. 4. Load address High byte using programming instruction 2c. 5. Load address Low byte using programming instruction 2d. 6.
PAGE 324
ATmega164A/PA/324A/PA/644A/PA/1284/P program counter after each word is read. Note that Capture-DR comes before the shift-DR state. Hence, the first byte which is shifted out contains valid data. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. 27.10.18Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed, See “Performing Chip Erase” on page 322. 1. Enter JTAG instruction PROG_COMMANDS. 2.
PAGE 325
ATmega164A/PA/324A/PA/644A/PA/1284/P 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 27-14 on page 308). 27.10.22Reading the Fuses and Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2.
PAGE 326
ATmega164A/PA/324A/PA/644A/PA/1284/P 28. Electrical characteristics (TA = -40°C to 85°C) Absolute maximum ratings* *NOTICE: Operating temperature ................................... -55C to +125C Storage temperature ...................................... -65°C to +150°C Voltage on any pin except RESET with respect to ground................................-0.5V to VCC + 0.5V Voltage on RESET with respect to ground...... -0.5V to +13.0V Maximum operating voltage ..........................................
PAGE 327
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-1. TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 5V IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 tACID Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Notes: Min. Vin = VCC/2 Typ. Max. Units <10 40 mV 50 nA -50 750 500 ns 1. “Max.” means the highest value where the pin is ensured to be read as low. 2. “Min.
PAGE 328
ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.1 ATmega164A DC characteristics Table 28-2. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Typ.(2) Max. Active 1MHz, VCC = 2V 0.3 0.55 Active 4MHz, VCC = 3V 1.4 3.5 Active 8MHz, VCC = 5V 4.8 12 Idle 1MHz, VCC = 2V 0.07 0.5 Idle 4MHz, VCC = 3V 0.25 1.5 Idle 8MHz, VCC = 5V 1.0 5.5 32kHz TOSC enabled, VCC = 1.8V 0.
PAGE 329
ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.3 ATmega324A DC characteristics Table 28-4. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Typ. (2) Max. Active 1MHz, VCC = 2V 0.3 0.55 Active 4MHz, VCC = 3V 1.5 3.5 Active 8MHz, VCC = 5V 5.2 12 Idle 1MHz, VCC = 2V 0.06 0.5 Idle 4MHz, VCC = 3V 0.35 1.5 Idle 8MHz, VCC = 5V 1.3 5.5 32kHz TOSC enabled, VCC = 1.8V 0.
PAGE 330
ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.5 ATmega644A DC characteristics Table 28-6. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Typ. (2) Max. Active 1MHz, VCC = 2V 0.38 0.5 Active 4MHz, VCC = 3V 1.8 2.7 Active 8MHz, VCC = 5V 5.6 9.0 Idle 1MHz, VCC = 2V 0.06 0.15 Idle 4MHz, VCC = 3V 0.2 0.7 Idle 8MHz, VCC = 5V 1.1 2.5 32kHz TOSC enabled, VCC = 1.8V 0.
PAGE 331
ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.7 ATmega1284 DC characteristics Table 28-8. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Typ. (2) Max. Active 1MHz, VCC = 2V 0.38 0.55 Active 4MHz, VCC = 3V 1.8 3.5 Active 8MHz, VCC = 5V 5.6 12 Idle 1MHz, VCC = 2V 0.06 0.5 Idle 4MHz, VCC = 3V 0.2 1.5 Idle 8MHz, VCC = 5V 1.1 5.5 32kHz TOSC enabled, VCC = 1.8V 0.
PAGE 332
ATmega164A/PA/324A/PA/644A/PA/1284/P 28.2 Speed grades Maximum frequency is depending on VCC. As shown in Figure 28-1, the maximum frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Figure 28-1. Maximum frequency vs. VCC, ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P 20MHz 10MHz Safe operating area 4MHz 1.8V  2018 Microchip Technology Inc. 2.7V 4.5V Data Sheet Complete 5.
PAGE 333
ATmega164A/PA/324A/PA/644A/PA/1284/P 28.3 Clock characteristics Table 28-10. Calibration accuracy of internal RC oscillator Factory calibration User calibration Notes: Frequency VCC 8.0MHz 3V 7.3 - 8.1MHz 1.8 - 5.5V (1) Temperature Calibration accuracy 25C ±10% -40C - 85C ±1% 1. Voltage range for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. 28.3.1 External clock drive waveforms Figure 28-2. External clock drive waveforms. V IH1 V IL1 28.3.2 External clock drive Table 28-11.
PAGE 334
ATmega164A/PA/324A/PA/644A/PA/1284/P 28.4 System and reset characteristics Table 28-12. Symbol Reset, Brown-out and Internal Voltage Reference characteristics Parameter Condition Power-on Reset Threshold Voltage (rising) VPOT Power-on Reset Threshold Voltage (falling) VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin VHYST (1) Min. Typ. Max. 1.1 1.4 1.6 0.6 1.3 1.6 0.2VCC Units V 0.9VCC 2.
PAGE 335
ATmega164A/PA/324A/PA/644A/PA/1284/P 28.6 SPI timing characteristics See Figure 28-3 on page 335 and Figure 28-4 on page 336 for details. Table 28-15. SPI timing parameters Description Mode 1 SCK period Master See Table 18-5 on page 173 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
PAGE 336
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 28-4. SPI interface timing requirements (Slave mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 28.7 17 MSB ... LSB X Two-wire Serial Interface Characteristics Table 28-16 describes the requirements for devices connected to the two-wire Serial Bus.
PAGE 337
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-16. two-wire serial bus requirements (Continued) Symbol Parameter tHIGH High period of the SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition tBUF Bus free time between a STOP and START condition Notes: 1. 2. 3. 4. 5. Condition Min. Max. fSCL  100kHz 4.0 – fSCL > 100kHz 0.6 – fSCL  100kHz 4.7 – fSCL > 100kHz 0.6 – fSCL  100kHz 0 3.
PAGE 338
ATmega164A/PA/324A/PA/644A/PA/1284/P 28.8 ADC characteristics Table 28-17. Symbol ADC characteristics, single ended channel Typ. (1) Max. (1) Condition Resolution Single Ended Conversion 10 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 1.9 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1MHz 3.25 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz Noise Reduction Mode 1.
PAGE 339
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-18. ADC characteristics, differential channels Symbol Parameter Resolution Absolute Accuracy (Including INL, DNL Quantization Error and Offset Error) Integral Non-linearity (INL) Differential Non-linearity (DNL)  2018 Microchip Technology Inc. Condition Min. (1) Typ.
PAGE 340
ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-18. ADC characteristics, differential channels (Continued) Symbol Parameter Condition Min. (1) Typ. (1) Max. (1) Units Gain = 1× 18 VCC = 5V, VREF = 4V ADC clock = 200kHz Gain = 10× Gain Error 19 VCC = 5V, VREF = 4V ADC clock = 200kHz Gain = 200× 1.
PAGE 341
ATmega164A/PA/324A/PA/644A/PA/1284/P 29. Electrical Characteristics - TA = -40°C to 105°C Absolute Maximum Ratings* *NOTICE: Operating Temperature .................................. -55C to +125C Storage Temperature...................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................ -0.5V to VCC+0.5V Voltage on RESET with respect to Ground ..... -0.5V to +13.0V Maximum Operating Voltage.............................................
PAGE 342
ATmega164A/PA/324A/PA/644A/PA/1284/P Note: 1. “Max" means the highest value where the pin is ensured to be read as low 2. “Min" means the lowest value where the pin is ensured to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1.)The sum of all IOL, for ports PB0-PB7, XTAL2, PD0-PD7 should not exceed 100 mA. 2.
PAGE 343
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1.3 ATmega644PA DC Characteristics Table 29-3. Symbol TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-down mode(2) Notes: Condition Min. Typ. Max. Units Active 1 MHz, VCC = 2V 0.7 mA Active 4 MHz, VCC = 3V 3 mA Active 8 MHz, VCC = 5V 11 mA Idle 1 MHz, VCC = 2V 0.17 mA Idle 4 MHz, VCC = 3V 0.
PAGE 344
ATmega164A/PA/324A/PA/644A/PA/1284/P 30. Typical characteristics -TA = -40°C to 85°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source.
PAGE 345
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-2. ATmega164A: Active supply current vs. frequency (1 - 20MHz) 12 5.5V 10 5.0V 4.5V ICC [mA] 8 4.0V 6 4 3.3V 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] ATmega164A: Active supply current vs. VCC (internal RC oscillator, 8MHz) Figure 30-3. 6 85°C 25°C -40°C 5 ICC [mA] 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 346
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-4. ATmega164A: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.2 85°C 25°C -40°C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] ATmega164A: Active supply current vs. VCC (internal RC oscillator, 128kHz) Figure 30-5. 0.25 -40°C 25°C 85°C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 347
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.2 Idle supply current Figure 30-6. ATmega164A: Idle supply current vs. VCC (0.1 - 1.0MHz) 0.20 5.5V 5.0V 4.5V 0.15 ICC [mA] 4.0V 3.3V 0.10 2.7V 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] ATmega164A: Idle supply current vs. VCC (1 - 20MHz) Figure 30-7. 3.0 5.5V 2.5 5.0V ICC [mA] 2.0 4.5V 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz]  2018 Microchip Technology Inc.
PAGE 348
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-8. ATmega164A: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.2 85°C 25°C -40°C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] ATmega164A: Idle supply current vs. VCC (internal RC oscillator, 1MHz) Figure 30-9. 0.35 -40°C 25°C 85°C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 349
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-10. ATmega164A: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40°C 0.10 25°C 85°C ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 350
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 56 for details. Table 30-1.
PAGE 351
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.4 Power-down supply current Figure 30-11. ATmega164A: Power-down supply current vs. VCC (watchdog timer disabled) 1.6 85°C 1.4 1.2 ICC [µA] 1.0 0.8 0.6 0.4 25°C -40°C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-12. ATmega164A: Power-down supply current vs. VCC (watchdog timer enabled) 10 -40°C 25°C 85°C ICC [µA] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 352
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.5 Power-save supply current Figure 30-13. ATmega164A: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 1.8 1.5 25°C ICC [µA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.1.6 Standby supply current Figure 30-14. ATmega164A: Standby supply current vs. VCC (watchdog timer disabled) 0.20 6MHz_xtal 6MHz_res 0.18 0.16 ICC [mA] 0.14 4MHz_res 4MHz_xtal 0.12 0.
PAGE 353
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.7 Pin pull-up Figure 30-15. ATmega164A: I/O pin pull-up resistor current vs. Input voltage (VCC = 1.8V) 50 45 40 IOP [µA] 35 30 25 20 15 25°C 85°C -40°C 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 30-16. ATmega164A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [µA] 50 40 30 20 25°C 85°C -40°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V]  2018 Microchip Technology Inc.
PAGE 354
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-17. ATmega164A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [µA] 100 80 60 40 25°C 20 85°C -40°C 0 0 1 2 3 4 5 6 VOP [V] Figure 30-18. ATmega164A: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 35 30 IRESET [µA] 25 20 15 10 25°C -40°C 85°C 5 0 0 0.5 1.0 1.5 2.0 VRESET [V]  2018 Microchip Technology Inc.
PAGE 355
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-19. ATmega164A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-20. ATmega164A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [µA] 80 60 40 25°C -40°C 85°C 20 0 0 1 2 3 4 5 6 VRESET [V]  2018 Microchip Technology Inc.
PAGE 356
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.8 Pin driver strength Figure 30-21. ATmega164A: I/O pin output voltage vs. sink current (VCC = 3V) 1.0 85°C 0.8 25°C VOL [V] 0.6 -40°C 0.4 0.2 0 0 4 8 12 16 20 IOL [mA] Figure 30-22. ATmega164A: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 4 8 12 16 20 IOL [mA]  2018 Microchip Technology Inc.
PAGE 357
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-23. ATmega164A: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 4 8 12 16 20 IOH [mA] Figure 30-24. ATmega164A: I/O pin output voltage vs. source current (VCC = 5V) 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 0 4 8 12 16 20 IOH [mA]  2018 Microchip Technology Inc.
PAGE 358
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.9 Pin threshold and hysteresis Figure 30-25. ATmega164A: I/O pin input threshold vs. VCC (VIH I/O pin read as ‘1’) 3.0 85°C 25°C -40°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-26. ATmega164A: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 359
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-27. ATmega164A: I/O pin input hysteresis vs. VCC 0.6 -40°C 25°C 85°C Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-28. ATmega164A: Reset pin input threshold vs. VCC (VIH I/O pin read as ‘1’) 2.5 -40°C 25°C 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 360
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-29. ATmega164A: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-30. ATmega164A: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 361
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.10 BOD threshold Figure 30-31. ATmega164A: BOD threshold vs. temperature (VBOT = 4.3V) 4.34 Rising Vcc 4.32 Threshold [V] 4.30 4.28 4.26 Falling Vcc 4.24 4.22 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 70 80 90 Temperature [°C] Figure 30-32. ATmega164A: BOD threshold vs. temperature (VBOT = 2.7V) 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.
PAGE 362
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-33. ATmega164A: BOD threshold vs. temperature (VBOT = 1.8V) 1.850 Rising Vcc 1.845 1.840 Threshold [V] 1.835 1.830 1.825 1.820 1.815 Falling Vcc 1.810 1.805 1.80 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-34. ATmega164A: Calibrated bandgap voltage vs. VCC 1.109 1.107 Bandgap voltage [V] 1.105 1.103 25°C 85°C 1.101 1.099 1.097 1.095 1.093 1.091 1.5 -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 363
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-35. ATmega164A: Bandgap voltage vs. temperature. 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 30.1.11 Internal oscillator speed Figure 30-36. ATmega164A: Watchdog oscillator frequency vs. temperature 134 132 FRC [kHz] 130 128 126 2.1V 2.7V 3.3V 4.0V 5.
PAGE 364
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-37. ATmega164A: Watchdog oscillator frequency vs. VCC 135 132 FRC [kHz] -40°C 129 25°C 126 123 85°C 120 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-38. ATmega164A: Calibrated 8MHz RC oscillator vs. VCC 8.4 85°C 8.2 FRC [MHz] 8.0 25°C 7.8 -40°C 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 365
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-39. ATmega164A: Calibrated 8MHz RC oscillator vs. temperature 8.3 5.0V 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-40. ATmega164A: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85°C 25°C -40°C 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1]  2018 Microchip Technology Inc.
PAGE 366
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.12 Current consumption of peripheral units Figure 30-41. ATmega164A: ADC current vs. VCC (AREF = AVCC) 320 -40°C 85°C 25°C 280 240 ICC [µA] 200 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-42. ATmega164A: Analog comparator current vs. VCC 100 90 -40°C 80 25°C 85°C ICC [µA] 70 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 367
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-43. ATmega164A: AREF external reference current vs. VCC 200 25°C 85°C -40°C ICC [µA] 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-44. ATmega164A: Brownout detector current vs. VCC 27 85°C 25°C -40°C 24 21 ICC [µA] 18 15 12 9 6 3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 368
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-45. ATmega164A: Programming current vs. VCC 12 -40°C 25°C 85°C 10 ICC [mA] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-46. ATmega164A: Watchdog timer current vs. VCC 9 -40°C 8 25°C 85°C 7 ICC [µA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 369
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.1.13 Current consumption in reset and reset pulsewidth Figure 30-47. ATmega164A: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 0.08 5.0V ICC [mA] 4.5V 0.06 4.0V 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.2 0.4 0.6 0.8 1.0 Frequency [MHz] Figure 30-48. ATmega164A: Reset supply current vs. frequency (1 - 20MHz) 1.8 5.5V 1.5 5.0V 4.5V ICC [mA] 1.2 0.9 4.0V 0.6 3.3V 0.3 2.7V 1.
PAGE 370
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-49. ATmega164A: Minimum reset pulsewidth vs. VCC 1600 1400 Pulsewidth [ns] 1200 1000 800 600 400 85°C 25°C -40°C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 371
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2 ATmega164PA typical characteristics - TA = -40°C to 85°C 30.2.1 Active supply current Figure 30-50. ATmega164PA: Active supply current vs. low frequency (0.1 - 1.0MHz) 1.2 5.5V 1.0 5.0V ICC [mA] 0.8 4.5V 4.0V 0.6 3.3V 0.4 2.7V 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-51. ATmega164PA: Active supply current vs. frequency (1 - 20MHz) 12 5.5V 10 5.0V 4.5V ICC [mA] 8 4.0V 6 4 3.3V 2.7V 2 1.
PAGE 372
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-52. ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 8MHz) 6 85°C 25°C -40°C 5 ICC [mA] 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-53. ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.2 85°C 25°C -40°C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 373
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-54. ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.25 -40°C 25°C 85°C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.2.2 Idle supply current Figure 30-55. ATmega164PA: Idle supply current vs. VCC (0.1 - 1.0MHz) 0.20 5.5V 5.0V 4.5V 0.15 ICC [mA] 4.0V 3.3V 0.10 2.7V 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz]  2018 Microchip Technology Inc.
PAGE 374
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-56. ATmega164PA: Idle supply current vs. VCC (1 - 20MHz) 3.0 5.5V 2.5 5.0V ICC [mA] 2.0 4.5V 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-57. ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.2 85°C 25°C -40°C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 375
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-58. ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 0.35 -40°C 25°C 85°C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-59. ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40°C 0.10 25°C 85°C ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 376
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 56 for details. Table 30-3.
PAGE 377
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.4 Power-down supply current Figure 30-60. ATmega164PA: Power-down supply current vs. VCC (watchdog timer disabled) 1.6 85°C 1.4 1.2 ICC [µA] 1.0 0.8 0.6 0.4 25°C -40°C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-61. ATmega164PA: Power-down supply current vs. VCC (watchdog timer enabled) 10 -40°C 25°C 85°C ICC [µA] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 378
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.5 Power-save supply current Figure 30-62. ATmega164PA: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 1.8 1.5 25°C ICC [µA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.2.6 Standby supply current Figure 30-63. ATmega164PA: Standby supply current vs. VCC (watchdog timer disabled) 0.20 6MHz_xtal 6MHz_res 0.18 0.16 ICC [mA] 0.14 4MHz_res 4MHz_xtal 0.12 0.
PAGE 379
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.7 Pin pull-up Figure 30-64. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 50 45 40 IOP [µA] 35 30 25 20 15 25°C 85°C -40°C 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 30-65. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [µA] 50 40 30 20 25°C 85°C -40°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V]  2018 Microchip Technology Inc.
PAGE 380
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-66. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [µA] 100 80 60 40 25°C 20 85°C -40°C 0 0 1 2 3 4 5 6 VOP [V] Figure 30-67. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 35 30 IRESET [µA] 25 20 15 10 25°C -40°C 85°C 5 0 0 0.5 1.0 1.5 2.0 VRESET [V]  2018 Microchip Technology Inc.
PAGE 381
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-68. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-69. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [µA] 80 60 40 25°C -40°C 85°C 20 0 0 1 2 3 4 5 6 VRESET [V]  2018 Microchip Technology Inc.
PAGE 382
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.8 Pin driver strength Figure 30-70. ATmega164PA: I/O pin output voltage vs. sink current (VCC = 3V) 1.0 85°C 0.8 25°C VOL [V] 0.6 -40°C 0.4 0.2 0 0 4 8 12 16 20 IOL [mA] Figure 30-71. ATmega164PA: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 4 8 12 16 20 IOL [mA]  2018 Microchip Technology Inc.
PAGE 383
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-72. ATmega164PA: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 4 8 12 16 20 IOH [mA] Figure 30-73. ATmega164PA: I/O pin output voltage vs. source current (VCC = 5V) 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 0 4 8 12 16 20 IOH [mA]  2018 Microchip Technology Inc.
PAGE 384
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.9 Pin threshold and hysteresis Figure 30-74. ATmega164PA: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) 3.0 85°C 25°C -40°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-75. ATmega164PA: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 385
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-76. ATmega164PA: I/O pin input hysteresis vs. VCC 0.6 -40°C 25°C 85°C Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-77. ATmega164PA: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) 2.5 -40°C 25°C 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 386
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-78. ATmega164PA: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-79. ATmega164PA: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 387
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.10 BOD threshold Figure 30-80. ATmega164PA: BOD threshold vs. temperature (VBOT = 4.3V) 4.34 Rising Vcc 4.32 Threshold [V] 4.30 4.28 4.26 Falling Vcc 4.24 4.22 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 80 90 Temperature [°C] Figure 30-81. ATmega164PA: BOD threshold vs. temperature (VBOT = 2.7V) 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.
PAGE 388
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-82. ATmega164PA: BOD threshold vs. temperature (VBOT = 1.8V) 1.850 Rising Vcc 1.845 1.840 Threshold [V] 1.835 1.830 1.825 1.820 1.815 Falling Vcc 1.810 1.805 1.80 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-83. ATmega164PA: Calibrated bandgap voltage vs. VCC 1.109 1.107 Bandgap voltage [V] 1.105 1.103 25°C 85°C 1.101 1.099 1.097 1.095 1.093 1.091 1.5 -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 389
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-84. ATmega164PA: Bandgap voltage vs. temperature 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 30.2.11 Internal oscillator speed Figure 30-85. ATmega164PA: Watchdog oscillator frequency vs. temperature 134 132 FRC [kHz] 130 128 126 2.1V 2.7V 3.3V 4.0V 5.
PAGE 390
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-86. ATmega164PA: Watchdog oscillator frequency vs. VCC 135 132 FRC [kHz] -40°C 129 25°C 126 123 85°C 120 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-87. ATmega164PA: Calibrated 8MHz RC oscillator vs. VCC 8.4 85°C 8.2 FRC [MHz] 8.0 25°C 7.8 -40°C 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 391
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-88. ATmega164PA: Calibrated 8MHz RC oscillator vs. temperature 8.3 5.0V 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-89. ATmega164PA: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85°C 25°C -40°C 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1]  2018 Microchip Technology Inc.
PAGE 392
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.12 Current consumption of peripheral units Figure 30-90. ATmega164PA: ADC current vs. VCC (AREF = AVCC) 320 -40°C 85°C 25°C 280 240 ICC [µA] 200 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-91. ATmega164PA: Analog comparator current vs. VCC 100 90 -40°C 80 25°C 85°C ICC [µA] 70 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 393
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-92. ATmega164PA: AREF external reference current vs. VCC 200 25°C 85°C -40°C ICC [µA] 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-93. ATmega164PA: Brownout detector current vs. VCC 27 85°C 25°C -40°C 24 21 ICC [µA] 18 15 12 9 6 3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 394
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-94. ATmega164PA: Programming current vs. VCC 12 -40°C 25°C 85°C 10 ICC [mA] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-95. ATmega164PA: Watchdog timer current vs. VCC 9 -40°C 8 25°C 85°C 7 ICC [µA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 395
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.2.13 Current consumption in reset and reset pulsewidth Figure 30-96. ATmega164PA: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 0.08 5.0V ICC [mA] 4.5V 0.06 4.0V 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.2 0.4 0.6 0.8 1.0 Frequency [MHz] Figure 30-97. ATmega164PA: Reset supply current vs. frequency (1 - 20MHz) 1.8 5.5V 1.5 5.0V 4.5V ICC [mA] 1.2 0.9 4.0V 0.6 3.3V 0.3 2.7V 1.
PAGE 396
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-98. ATmega164PA: Minimum reset pulsewidth vs. VCC 1600 1400 Pulsewidth [ns] 1200 1000 800 600 400 85°C 25°C -40°C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 397
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3 ATmega324A typical characteristics - TA = -40°C to 85°C 30.3.1 Active supply current Figure 30-99. ATmega324A: Active supply current vs. low frequency (0.1 - 1.0MHz) I CC [mA] 1.2 5.5V 1.0 5.0V 0.8 4.5V 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-100. ATmega324A: Active supply current vs. frequency (1 - 20MHz) ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.
PAGE 398
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-101. ATmega324A: Active supply current vs. VCC (internal RC oscillator, 8MHz) 7 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-102. ATmega324A: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.6 85°C 25°C -40°C ICC [mA] 1.2 0.8 0.4 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 399
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-103. ATmega324A: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.25 -40°C 25°C 85°C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.3.2 Idle supply current Figure 30-104. ATmega324A: Idle supply current vs. VCC (0.1 - 1.0MHz) 5.5V 0.25 5.0V 0.20 4.5V ICC [mA] 4.0V 0.15 3.3V 2.7V 0.10 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
PAGE 400
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-105. ATmega324A: Idle supply current vs. VCC (1 - 20MHz) 4 5.5V 5.0V 3 ICC [mA] 4.5V 2 4.0V 3.3V 1 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-106. ATmega324A: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.8 85°C 25°C -40°C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 401
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-107. ATmega324A: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 85°C 25°C -40°C 0.6 0.5 ICC [mA] 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-108. ATmega324A: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40°C 25°C 85°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 402
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 56 for details. Table 30-5.
PAGE 403
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.4 Power-down supply current Figure 30-109. ATmega324A: Power-down supply current vs. VCC (watchdog timer disabled) 1.2 85°C 1.0 ICC [µA] 0.8 0.6 0.4 25°C -40°C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-110. ATmega324A: Power-down supply current vs. VCC (watchdog timer enabled) 10 -40°C 85°C 25°C 8 ICC [µA] 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 404
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.5 Power-save supply current Figure 30-111. ATmega324A: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 2.50 85°C ICC [µA] 2.00 1.50 25°C -40°C 1.00 0.50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.3.6 Standby supply current Figure 30-112. ATmega324A: Standby supply current vs. VCC (watchdog timer disabled) 0.18 6MHz_res 6MHz_xtal 0.16 0.14 4MHz_res 4MHz_xtal ICC [mA] 0.12 0.10 2MHz_res 0.
PAGE 405
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.7 Pin pull-up Figure 30-113. ATmega324A: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 50 40 IOP [µA] 30 20 25°C -40°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 30-114. ATmega324A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [µA] 50 40 30 25°C 20 85°C 10 -40°C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V]  2018 Microchip Technology Inc.
PAGE 406
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-115. ATmega324A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [µA] 100 80 60 25°C 40 85°C 20 -40°C 0 0 1 2 3 4 5 6 VOP [V] Figure 30-116. ATmega324A: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 35 30 IRESET [µA] 25 20 15 10 25°C 5 -40°C 85°C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VRESET [V]  2018 Microchip Technology Inc.
PAGE 407
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-117. ATmega324A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-118. ATmega324A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [µA] 80 60 40 25°C 20 -40°C 85°C 0 0 1 2 3 4 5 6 VRESET [V]  2018 Microchip Technology Inc.
PAGE 408
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.8 Pin driver strength Figure 30-119. ATmega324A: I/O pin output voltage vs. sink current (VCC = 3V) 1.0 85°C 0.8 25°C VOL [V] 0.6 -40°C 0.4 0.2 0 5 8 11 14 17 20 IOL [mA] Figure 30-120. ATmega324A: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 5 8 11 14 17 20 IOL [mA]  2018 Microchip Technology Inc.
PAGE 409
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-121. ATmega324A: I/O pin output voltage vs. source current (VCC = 3V) 3.0 2.5 -40°C 25°C 85°C VOH [V] 2.0 1.5 1.0 0.5 0 5 8 11 14 17 20 IOH [mA] Figure 30-122. ATmega324A: I/O pin output voltage vs. source current (VCC = 5V) 4.9 4.8 VOH [V] 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 5 8 11 14 17 20 IOH [mA]  2018 Microchip Technology Inc.
PAGE 410
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.9 Pin threshold and hysteresis Figure 30-123. ATmega324A: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) 85°C 3.0 -40°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-124. ATmega324A: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 411
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-125. ATmega324A: I/O pin input hysteresis vs. VCC 0.6 85°C 25°C 0.5 Input hysteresis [mV] -40°C 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-126. ATmega324A: Reset pin input , threshold vs. VCC (VIH , I/O pin read as ‘1’) -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 412
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-127. ATmega324A: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) -40°C 25°C 2.5 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-128. ATmega324A: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 413
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.10 BOD threshold Figure 30-129. ATmega324A: BOD threshold vs. temperature (VBOT = 4.3V) 4.40 Rising Vcc 4.38 Threshold [V] 4.36 4.34 4.32 Falling Vcc 4.30 4.28 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 30-130. ATmega324A: BOD threshold vs. temperature (VBOT = 2.7V) 2.80 Rising Vcc 2.78 Threshold [V] 2.76 2.74 Falling Vcc 2.72 2.70 2.68 2.66 -40 -20 0 20 40 60 80 100 Temperature [°C]  2018 Microchip Technology Inc.
PAGE 414
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-131. ATmega324A: BOD threshold vs. temperature (VBOT = 1.8V) 1.86 Rising Vcc Threshold [V] 1.84 1.82 Falling Vcc 1.80 1.78 1.76 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 30-132. ATmega324A: Calibrated bandgap voltage vs. VCC 1.098 1.096 Bandgap voltage [V] 1.094 1.092 85°C 25°C 1.090 1.088 1.086 1.084 1.082 1.080 -40°C 1.078 1.076 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V]  2018 Microchip Technology Inc.
PAGE 415
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-133. ATmega324A: Bandgap voltage vs. temperature 1.097 1.8V 3.6V 2.7V 4.5V 1.095 Bandgap voltage [V] 1.093 1.091 5.5V 1.089 1.087 1.085 1.083 1.081 1.079 1.077 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 30.3.11 Internal oscillator speed Figure 30-134. ATmega324A: Watchdog oscillator frequency vs. temperature 122 FRC [kHz] 119 116 2.1V 2.7V 3.3V 4.0V 5.
PAGE 416
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-135. ATmega324A: Watchdog oscillator frequency vs. VCC 123 -40°C FRC [kHz] 120 25°C 117 114 85°C 111 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-136. ATmega324A: Calibrated 8MHz RC oscillator vs. VCC 8.6 85°C 8.2 FRC [MHz] 25°C 7.8 -40°C 7.4 7.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 417
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-137. ATmega324A: Calibrated 8MHz RC oscillator vs. temperature 8.6 5.0V 3.0V FRC [MHz] 8.3 8.0 7.7 7.4 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 30-138. ATmega324A: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85°C 25°C -40°C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1)  2018 Microchip Technology Inc.
PAGE 418
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.12 Current consumption of peripheral units Figure 30-139. ATmega324A: ADC current vs. VCC (AREF = AVCC) 300 25°C 85°C -40°C 250 ICC [µA] 200 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-140. ATmega324A: Analog comparator current vs. VCC 90 -40°C 80 25°C 70 85°C ICC [µA] 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 419
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-141. ATmega324A: AREF external reference current vs. VCC 25°C 85°C -40°C 200 160 ICC [µA] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-142. ATmega324A: Brownout detector current vs. VCC 25 85°C 25°C -40°C 20 ICC [µA] 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 420
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-143. ATmega324A: Programming current vs. VCC 14 25°C -40°C 85°C 12 ICC [mA] 10 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-144. ATmega324A: Watchdog timer current vs. VCC 9 -40°C 25°C 85°C ICC [µA] 7 5 3 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 421
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.3.13 Current consumption in reset and reset pulsewidth Figure 30-145. ATmega324A: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.14 5.5V 0.12 5.0V 0.10 I CC [mA] 4.5V 0.08 4.0V 0.06 3.3V 2.7V 0.04 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-146. ATmega324A: Reset supply current vs. frequency (1 - 20MHz) 2.5 5.5V 2.0 5.0V 4.5V I CC [mA] 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.
PAGE 422
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-147. ATmega324A: Minimum reset pulsewidth vs. VCC 1800 1500 Pulsewidth [ns] 1200 900 600 85°C 25°C -40°C 300 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V CC [V]  2018 Microchip Technology Inc.
PAGE 423
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4 ATmega324PA typical characteristics - TA = -40°C to 85°C 30.4.1 Active supply current Figure 30-148. ATmega324PA: Active supply current vs. low frequency (0.1 - 1.0MHz) I CC [mA] 1.2 5.5V 1.0 5.0V 0.8 4.5V 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-149. ATmega324PA: Active supply current vs. frequency (1 - 20MHz) ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.
PAGE 424
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-150. ATmega324PA: Active supply current vs. VCC (internal RC oscillator, 8MHz) 7 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-151. ATmega324PA: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.6 85°C 25°C -40°C ICC [mA] 1.2 0.8 0.4 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 425
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-152. ATmega324PA: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.25 -40°C 25°C 85°C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.4.2 Idle supply current Figure 30-153. ATmega324PA: Idle supply current vs. VCC (0.1 - 1.0MHz) 5.5V 0.25 5.0V 0.20 4.5V ICC [mA] 4.0V 0.15 3.3V 2.7V 0.10 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
PAGE 426
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-154. ATmega324PA: Idle supply current vs. VCC (1 - 20MHz) 4 5.5V 5.0V 3 ICC [mA] 4.5V 2 4.0V 3.3V 1 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-155. ATmega324PA: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.8 85°C 25°C -40°C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 427
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-156. ATmega324PA: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 85°C 25°C -40°C 0.6 0.5 ICC [mA] 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-157. ATmega324PA: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40°C 25°C 85°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 428
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 56 for details. Table 30-7.
PAGE 429
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.4 Power-down Supply Current Figure 30-158. ATmega324PA: Power-down supply current vs. VCC (watchdog timer disabled) 1.2 85°C 1.0 ICC [µA] 0.8 0.6 0.4 25°C -40°C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-159. ATmega324PA: Power-down supply current vs. VCC (watchdog timer enabled) 10 -40°C 85°C 25°C 8 ICC [µA] 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 430
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.5 Power-save supply current Figure 30-160. ATmega324PA: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 2.50 85°C ICC [µA] 2.00 1.50 25°C -40°C 1.00 0.50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.4.6 Standby supply current Figure 30-161. ATmega324PA: Standby supply current vs. VCC (watchdog timer disabled) 0.18 6MHz_res 6MHz_xtal 0.16 0.14 4MHz_res 4MHz_xtal ICC [mA] 0.12 0.
PAGE 431
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.7 Pin pull-up Figure 30-162. ATmega324PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 50 40 IOP [µA] 30 20 25°C -40°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 30-163. ATmega324PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [µA] 50 40 30 25°C 20 85°C 10 -40°C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V]  2018 Microchip Technology Inc.
PAGE 432
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-164. ATmega324PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [µA] 100 80 60 25°C 40 85°C 20 -40°C 0 0 1 2 3 4 5 6 VOP [V] Figure 30-165. ATmega324PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 35 30 IRESET [µA] 25 20 15 10 25°C 5 -40°C 85°C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VRESET [V]  2018 Microchip Technology Inc.
PAGE 433
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-166. ATmega324PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-167. ATmega324PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [µA] 80 60 40 25°C 20 -40°C 85°C 0 0 1 2 3 4 5 6 VRESET [V]  2018 Microchip Technology Inc.
PAGE 434
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.8 Pin driver strength Figure 30-168. ATmega324PA: I/O pin output voltage vs. sink current (VCC = 3V) 1.0 85°C 0.8 25°C VOL [V] 0.6 -40°C 0.4 0.2 0 5 8 11 14 17 20 IOL [mA] Figure 30-169. ATmega324PA: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 5 8 11 14 17 20 IOL [mA]  2018 Microchip Technology Inc.
PAGE 435
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-170. ATmega324PA: I/O pin output voltage vs. source current (VCC = 3V) 3.0 2.5 -40°C 25°C 85°C VOH [V] 2.0 1.5 1.0 0.5 0 5 8 11 14 17 20 IOH [mA] Figure 30-171. ATmega324PA: I/O pin output voltage vs. source current (VCC = 5V) 4.9 4.8 VOH [V] 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 5 8 11 14 17 20 IOH [mA]  2018 Microchip Technology Inc.
PAGE 436
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.9 Pin threshold and hysteresis Figure 30-172. ATmega324PA: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) 85°C 3.0 -40°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-173. ATmega324PA: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 437
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-174. ATmega324PA: I/O pin input hysteresis vs. VCC 0.6 85°C 25°C 0.5 Input hysteresis [mV] -40°C 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-175. ATmega324PA: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) , -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 438
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-176. ATmega324PA: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) -40°C 25°C 2.5 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-177. ATmega324PA: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 439
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.10 BOD threshold Figure 30-178. ATmega324PA: BOD threshold vs. temperature (VBOT = 4.3V). 4.40 Rising Vcc 4.38 Threshold [V] 4.36 4.34 4.32 Falling Vcc 4.30 4.28 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 30-179. ATmega324PA: BOD threshold vs. temperature (VBOT = 2.7V) 2.80 Rising Vcc 2.78 Threshold [V] 2.76 2.74 Falling Vcc 2.72 2.70 2.68 2.66 -40 -20 0 20 40 60 80 100 Temperature [°C]  2018 Microchip Technology Inc.
PAGE 440
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-180. ATmega324PA: BOD threshold vs. temperature (VBOT = 1.8V) 1.86 Rising Vcc Threshold [V] 1.84 1.82 Falling Vcc 1.80 1.78 1.76 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 30-181. ATmega324PA: Calibrated bandgap voltage vs. VCC 1.098 1.096 Bandgap voltage [V] 1.094 1.092 85°C 25°C 1.090 1.088 1.086 1.084 1.082 1.080 -40°C 1.078 1.076 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V]  2018 Microchip Technology Inc.
PAGE 441
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-182. ATmega324PA: Bandgap voltage vs. temperature 1.097 1.8V 3.6V 2.7V 4.5V 1.095 Bandgap voltage [V] 1.093 1.091 5.5V 1.089 1.087 1.085 1.083 1.081 1.079 1.077 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 30.4.11 Internal oscillator speed Figure 30-183. ATmega324PA: Watchdog oscillator frequency vs. temperature 122 FRC [kHz] 119 116 2.1V 2.7V 3.3V 4.0V 5.
PAGE 442
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-184. ATmega324PA: Watchdog oscillator frequency vs. VCC 123 -40°C FRC [kHz] 120 25°C 117 114 85°C 111 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-185. ATmega324PA: Calibrated 8MHz RC oscillator vs. VCC 8.6 85°C 8.2 FRC [MHz] 25°C 7.8 -40°C 7.4 7.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 443
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-186. ATmega324PA: Calibrated 8MHz RC oscillator vs. temperature 8.6 5.0V 3.0V FRC [MHz] 8.3 8.0 7.7 7.4 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 30-187. ATmega324PA: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85°C 25°C -40°C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1)  2018 Microchip Technology Inc.
PAGE 444
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.12 Current consumption of peripheral units Figure 30-188. ATmega324PA: ADC current vs. VCC (AREF = AVCC) 300 25°C 85°C -40°C 250 ICC [µA] 200 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-189. ATmega324PA: Analog comparator current vs. VCC 90 -40°C 80 25°C 70 85°C ICC [µA] 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 445
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-190. ATmega324PA: AREF external reference current vs. VCC 25°C 85°C -40°C 200 160 ICC [µA] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-191. ATmega324PA: Brownout detector current vs. VCC 25 85°C 25°C -40°C 20 ICC [µA] 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 446
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-192. ATmega324PA: Programming current vs. VCC 14 25°C -40°C 85°C 12 ICC [mA] 10 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-193. ATmega324PA: Watchdog timer current vs. VCC 9 -40°C 25°C 85°C ICC [µA] 7 5 3 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 447
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.4.13 Current consumption in reset and reset pulsewidth Figure 30-194. ATmega324PA: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.14 5.5V 0.12 5.0V 0.10 I CC [mA] 4.5V 0.08 4.0V 0.06 3.3V 2.7V 0.04 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-195. ATmega324PA: Reset supply current vs. frequency (1 - 20MHz) 2.5 5.5V 2.0 5.0V 4.5V I CC [mA] 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.
PAGE 448
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-196. ATmega324PA: Minimum reset pulsewidth vs. VCC 1800 1500 Pulsewidth [ns] 1200 900 600 85°C 25°C -40°C 300 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V CC [V]  2018 Microchip Technology Inc.
PAGE 449
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5 ATmega644A typical characteristics - TA = -40°C to 85°C 30.5.1 Active supply current Figure 30-197. ATmega644A: Active supply current vs. low frequency (0.1 - 1.0MHz) 1.2 5.5V 1.0 5.0V 4.5V ICC [mA] 0.8 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-198. ATmega644A: Active supply current vs. frequency (1 - 20MHz) ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.
PAGE 450
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-199. ATmega644A: Active supply current vs. VCC (internal RC oscillator, 8MHz) 7 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-200. ATmega644A: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.4 85°C 25°C -40°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 451
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-201. ATmega644A: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.22 -40°C 25°C 85°C 0.20 0.18 ICC [mA] 0.16 0.14 0.12 0.10 0.08 0.06 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.5.2 Idle supply current Figure 30-202. ATmega644A: Idle supply current vs. VCC (0.1 - 1.0MHz) 0.24 5.5V 0.20 5.0V 4.5V 4.0V ICC [mA] 0.16 3.3V 2.7V 0.12 0.08 1.8V 0.04 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
PAGE 452
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-203. ATmega644A: Idle supply current vs. VCC (1 - 20MHz) 3.0 5.5V 5.0V 2.5 4.5V ICC [mA] 2.0 4.0V 1.5 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-204. ATmega644A: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.4 85°C 25°C -40°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 453
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-205. ATmega644A: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 0.35 85°C 25°C -40°C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-206. ATmega644A: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40°C 25°C 85°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 454
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 56 for details. Table 30-9.
PAGE 455
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.4 Power-down supply current Figure 30-207. ATmega644A: Power-down supply current vs. VCC (watchdog timer disabled) 2.5 85°C 2.0 ICC [µA] 1.5 1.0 0.5 25°C -40°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-208. ATmega644A: Power-down supply current vs. VCC (watchdog timer enabled) 9 85°C 8 -40°C 25°C ICC [µA] 7 6 5 4 3 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 456
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.5 Power-save supply current Figure 30-209. ATmega644A: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 2.5 85°C 2.0 Icc [µA] 1.5 1.0 0.5 25°C -40°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.5.6 Standby supply current Figure 30-210. ATmega644A: Standby supply current vs. VCC (watchdog timer disabled) 0.16 6MHz_res 6MHz_xtal 0.14 4MHz_res 0.12 4MHz_xtal ICC [mA] 0.10 0.08 2MHz_res 0.
PAGE 457
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.7 Pin pull-up Figure 30-211. ATmega644A: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 50 45 40 35 IOP [µA] 30 25 20 15 10 25°C 85°C -40°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VOP [V] Figure 30-212. ATmega644A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [µA] 50 40 30 20 25°C 85°C -40°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V]  2018 Microchip Technology Inc.
PAGE 458
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-213. ATmega644A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [µA] 100 80 60 40 25°C 85°C -40°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 30-214. ATmega644A: g Reset pull-uppresistor current vs. reset pin g (voltage (V ) CC = 1.8V) 35 30 IRESET [µA] 25 20 15 10 25°C -40°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VRESET [V]  2018 Microchip Technology Inc.
PAGE 459
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-215. ATmega644A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-216. ATmega644A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [µA] 80 60 40 25°C -40°C 85°C 20 0 0 1 2 3 4 5 VRESET [V]  2018 Microchip Technology Inc.
PAGE 460
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.8 Pin driver strength Figure 30-217. ATmega644A: I/O pin output voltage vs. sink current (VCC = 3V) 0.9 85°C 0.8 0.7 25°C 0.6 VOL [V] -40°C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-218. ATmega644A: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA]  2018 Microchip Technology Inc.
PAGE 461
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-219. ATmega644A: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 30-220. ATmega644A: I/O pin output voltage vs. source current (VCC = 5V) 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH [mA]  2018 Microchip Technology Inc.
PAGE 462
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.9 Pin threshold and hysteresis Figure 30-221. ATmega644A: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) 3.0 85°C -40°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-222. ATmega644A: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 463
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-223. ATmega644A: I/O pin input hysteresis vs. VCC 0.60 25°C 85°C -40°C 0.55 Input Hysteresis [mV] 0.50 0.45 0.40 0.35 0.30 0.25 0.20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-224. ATmega644A: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) 2.5 -40°C 25°C 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 464
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-225. ATmega644A: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-226. ATmega644A: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 465
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.10 BOD threshold Figure 30-227. ATmega644A: BOD threshold vs. temperature (VBOT = 4.3V) 4.35 Rising Vcc Threshold [V] 4.32 4.29 Falling Vcc 4.26 4.23 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 80 90 100 Temperature [°C] Figure 30-228. ATmega644A: BOD threshold vs. temperature (VBOT = 2.7V) 2.77 Rising Vcc 2.75 Threshold [V] 2.73 2.71 Falling Vcc 2.69 2.67 2.
PAGE 466
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-229. ATmega644A: BOD threshold vs. temperature (VBOT = 1.8V) 1.84 1.83 Rising Vcc Threshold [V] 1.82 1.81 1.80 Falling Vcc 1.79 1.78 1.77 1.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] Figure 30-230. ATmega644A: Calibrated bandgap voltage vs. VCC 1.086 1.084 Bandgap voltage [V] 1.082 85°C 25°C 1.080 1.078 1.076 1.074 1.072 1.070 1.068 1.066 1.5 -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 467
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-231. ATmega644A: Bandgap voltage vs. temperature 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 30.5.11 Internal oscillator speed Figure 30-232. ATmega644A: Watchdog oscillator frequency vs. temperature 119 118 117 116 FRC [kHz] 115 114 113 2.1V 112 2.7V 3.3V 4.0V 5.
PAGE 468
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-233. ATmega644A: Watchdog oscillator frequency vs. VCC 119 118 117 -40°C 116 FRC [kHz] 115 25°C 114 113 112 111 110 85°C 109 108 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-234. ATmega644A: Calibrated 8MHz RC oscillator vs. VCC 8.4 85°C 8.2 25°C FRC [MHz] 8.0 -40°C 7.8 7.6 7.4 7.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 469
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-235. ATmega644A: Calibrated 8MHz RC oscillator vs. temperature 8.4 5.0V 8.3 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 7.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature [°C] Figure 30-236. ATmega644A: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85°C 25°C -40°C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL [X1]  2018 Microchip Technology Inc.
PAGE 470
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.12 Current consumption of peripheral units Figure 30-237. ATmega644A: ADC current vs. VCC (AREF = AVCC) 250 25°C 85°C -40°C 200 ICC [µA] 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC [V] Figure 30-238. ATmega644A: Analog comparator current vs. VCC 90 -40°C 80 25°C 85°C ICC [µA] 70 60 50 40 30 20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 471
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-239. ATmega644A: AREF external reference current vs. VCC 200 25°C 85°C -40°C 160 ICC [µA] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-240. ATmega644A: Brownout detector current vs. VCC 24 85°C 22 25°C -40°C ICC [µA] 20 18 16 14 12 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 472
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-241. ATmega644A: Programming current vs. VCC -40°C 16 14 12 ICC [mA] 10 25°C 8 85°C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-242. ATmega644A: Watchdog timer current vs. VCC 9 8 -40°C 7 25°C 85°C ICC [µA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 473
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.5.13 Current consumption in reset and reset pulsewidth Figure 30-243. ATmega644A: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-244. ATmega644A: Reset supply current vs. frequency (1 - 20MHz) 2.00 5.5V 1.75 5.0V 1.50 4.5V ICC [mA] 1.25 1.00 4.0V 0.75 3.3V 0.50 2.7V 0.25 1.
PAGE 474
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-245. ATmega644A: Minimum reset pulsewidth vs. VCC 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 85°C 25°C -40°C 400 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 475
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6 ATmega644PA typical characteristics - TA = -40°C to 85°C 30.6.1 Active supply current Figure 30-246. ATmega644PA: Active supply current vs. low frequency (0.1 - 1.0MHz) 1.2 5.5V 1.0 5.0V 4.5V ICC [mA] 0.8 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-247. ATmega644PA: Active supply current vs. frequency (1 - 20MHz) ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.
PAGE 476
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-248. ATmega644PA: Active supply current vs. VCC (internal RC oscillator, 8MHz) 7 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-249. ATmega644PA: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.4 85°C 25°C -40°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 477
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-250. ATmega644PA: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.22 -40°C 25°C 85°C 0.20 0.18 ICC [mA] 0.16 0.14 0.12 0.10 0.08 0.06 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.6.2 Idle supply current Figure 30-251. ATmega644PA: Idle supply current vs. VCC (0.1 - 1.0MHz) 0.24 5.5V 0.20 5.0V 4.5V 4.0V ICC [mA] 0.16 3.3V 2.7V 0.12 0.08 1.8V 0.04 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
PAGE 478
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-252. ATmega644PA: Idle supply current vs. VCC (1 - 20MHz) 3.0 5.5V 5.0V 2.5 4.5V ICC [mA] 2.0 4.0V 1.5 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-253. ATmega644PA: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.4 85°C 25°C -40°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 479
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-254. ATmega644PA: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 0.35 85°C 25°C -40°C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-255. ATmega644PA: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40°C 25°C 85°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 480
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 56 for details. Table 30-11.
PAGE 481
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.4 Power-down supply current Figure 30-256. ATmega644PA: Power-down supply current vs. VCC (watchdog timer disabled) 2.5 85°C 2.0 ICC [µA] 1.5 1.0 0.5 25°C -40°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-257. ATmega644PA: Power-down supply current vs. VCC (watchdog timer enabled) 9 85°C 8 -40°C 25°C ICC [µA] 7 6 5 4 3 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 482
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.5 Power-save supply current Figure 30-258. ATmega644PA: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 2.5 85°C 2.0 Icc [µA] 1.5 1.0 0.5 25°C -40°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.6.6 Standby supply current Figure 30-259. ATmega644PA: Standby supply current vs. VCC (watchdog timer disabled) 0.16 6MHz_res 6MHz_xtal 0.14 4MHz_res 0.12 4MHz_xtal ICC [mA] 0.10 0.08 2MHz_res 0.
PAGE 483
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.7 Pin pull-up Figure 30-260. ATmega644PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 50 45 40 35 IOP [µA] 30 25 20 15 10 25°C 85°C -40°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VOP [V] Figure 30-261. ATmega644PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [µA] 50 40 30 20 25°C 85°C -40°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V]  2018 Microchip Technology Inc.
PAGE 484
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-262. ATmega644PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [µA] 100 80 60 40 25°C 85°C -40°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 30-263. ATmega644PA: Reset pull-up g p resistor current vs. reset gpin ( voltage) (VCC = 1.8V) 35 30 IRESET [µA] 25 20 15 10 25°C -40°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VRESET [V]  2018 Microchip Technology Inc.
PAGE 485
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-264. ATmega644PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-265. ATmega644PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [µA] 80 60 40 25°C -40°C 85°C 20 0 0 1 2 3 4 5 VRESET [V]  2018 Microchip Technology Inc.
PAGE 486
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.8 Pin driver strength Figure 30-266. ATmega644PA: I/O pin output voltage vs. sink current (VCC = 3V) 0.9 85°C 0.8 0.7 25°C 0.6 VOL [V] -40°C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-267. ATmega644PA: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA]  2018 Microchip Technology Inc.
PAGE 487
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-268. ATmega644PA: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 30-269. ATmega644PA: I/O pin output voltage vs. source current (VCC = 5V) 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH [mA]  2018 Microchip Technology Inc.
PAGE 488
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.9 Pin threshold and hysteresis Figure 30-270. ATmega644PA: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) 3.0 85°C -40°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-271. ATmega644PA: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 489
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-272. ATmega644PA: I/O pin input hysteresis vs. VCC 0.60 25°C 85°C -40°C 0.55 Input Hysteresis [mV] 0.50 0.45 0.40 0.35 0.30 0.25 0.20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-273. ATmega644PA: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) 2.5 -40°C 25°C 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 490
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-274. ATmega644PA: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-275. ATmega644PA: Reset pin input hysteresis vs. VCC 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 491
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.10 BOD threshold Figure 30-276. ATmega644PA: BOD threshold vs. temperature (VBOT = 4.3V) 4.35 Rising Vcc Threshold [V] 4.32 4.29 Falling Vcc 4.26 4.23 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 90 100 Temperature [°C] Figure 30-277. ATmega644PA: BOD threshold vs. temperature (VBOT = 2.7V) 2.77 Rising Vcc 2.75 Threshold [V] 2.73 2.71 Falling Vcc 2.69 2.67 2.
PAGE 492
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-278. ATmega644PA: BOD threshold vs. temperature (VBOT = 1.8V) 1.84 1.83 Rising Vcc Threshold [V] 1.82 1.81 1.80 Falling Vcc 1.79 1.78 1.77 1.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] Figure 30-279. ATmega644PA: Calibrated bandgap voltage vs. VCC 1.086 1.084 Bandgap voltage [V] 1.082 85°C 25°C 1.080 1.078 1.076 1.074 1.072 1.070 1.068 1.066 1.5 -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 493
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-280. ATmega324PA: Bandgap voltage vs. temperature 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 30.6.11 Internal oscillator speed Figure 30-281. ATmega644PA: Watchdog oscillator frequency vs. temperature 119 118 117 116 FRC [kHz] 115 114 113 2.1V 112 2.7V 3.3V 4.0V 5.
PAGE 494
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-282. ATmega644PA: Watchdog oscillator orequency vs. VCC 119 118 117 -40°C 116 FRC [kHz] 115 25°C 114 113 112 111 110 85°C 109 108 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-283. ATmega644PA: Calibrated 8MHz RC oscillator vs. VCC 8.4 85°C 8.2 25°C FRC [MHz] 8.0 -40°C 7.8 7.6 7.4 7.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 495
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-284. ATmega644PA: Calibrated 8MHz RC oscillator vs. temperature 8.4 5.0V 8.3 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 7.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature [°C] Figure 30-285. ATmega644PA: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85°C 25°C -40°C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL [X1]  2018 Microchip Technology Inc.
PAGE 496
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.12 Current consumption of peripheral units Figure 30-286. ATmega644PA: ADC current vs. VCC (AREF = AVCC) 250 25°C 85°C -40°C 200 ICC [µA] 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC [V] Figure 30-287. ATmega644PA: Analog comparator current vs. VCC 90 -40°C 80 25°C 85°C ICC [µA] 70 60 50 40 30 20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 497
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-288. ATmega644PA: AREF external reference current vs. VCC 200 25°C 85°C -40°C 160 ICC [µA] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-289. ATmega644PA: Brownout detector current vs. VCC 24 85°C 22 25°C -40°C ICC [µA] 20 18 16 14 12 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 498
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-290. ATmega644PA: Programming current vs. VCC -40°C 16 14 12 ICC [mA] 10 25°C 8 85°C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-291. ATmega644PA: Watchdog timer current vs. VCC 9 8 -40°C 7 25°C 85°C ICC [µA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 499
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.6.13 Current consumption in reset and reset pulsewidth Figure 30-292. ATmega644PA: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-293. ATmega644PA: Reset supply current vs. frequency (1 - 20MHz) 2.00 5.5V 1.75 5.0V 1.50 4.5V ICC [mA] 1.25 1.00 4.0V 0.75 3.3V 0.50 2.7V 0.25 1.
PAGE 500
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-294. ATmega644PA: Minimum reset pulsewidth vs. VCC 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 85°C 25°C -40°C 400 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 501
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7 ATmega1284 typical characteristics - TA = -40°C to 85°C 30.7.1 Active supply current ICC [mA] Figure 30-295. ATmega1284: Active supply current vs. low frequency (0.1 - 1.0MHz) 1.6 5.5V 1.4 5.0V 1.2 4.5V 1.0 4.0V 0.8 3.3V 0.6 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-296. ATmega1284: Active supply current vs. frequency (1 - 20MHz) 20 5.5V 18 5.0V 16 4.5V ICC [mA] 14 12 4.0V 10 8 3.
PAGE 502
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-297. ATmega1284: Active supply current vs. VCC (internal RC oscillator, 8MHz) 9 85°C 25°C -40°C 8 7 ICC [mA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-298. ATmega1284: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.8 85°C 25°C -40°C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 503
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-299. ATmega1284: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.28 -40°C 25°C 85°C 0.24 ICC [mA] 0.20 0.16 0.12 0.08 0.04 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.7.2 Idle supply current Figure 30-300. ATmega1284: Idle supply current vs. low frequency (0.1 - 1.0MHz) 0.24 5.5V 0.21 5.0V 0.18 4.5V 4.0V 3.6V ICC [mA] 0.15 0.12 2.7V 0.09 1.8V 0.06 0.03 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
PAGE 504
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-301. ATmega1284: Idle supply current vs. frequency (1 - 20MHz) 3.0 5.5V 2.5 5.0V 4.5V ICC [mA] 2.0 1.5 4.0V 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-302. ATmega1284: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.4 85°C 1.2 25°C -40°C ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 505
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-303. ATmega1284: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 0.42 85°C 25°C -40°C 0.36 ICC [mA] 0.30 0.24 0.18 0.12 0.06 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-304. ATmega1284: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40°C 85°C 25°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 506
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 56 for details. Table 30-13.
PAGE 507
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.4 Power-down supply current Figure 30-305. ATmega1284: Power-down supply current vs. VCC (watchdog timer disabled) 4.0 85°C 3.5 3.0 ICC [µA] 2.5 2.0 1.5 1.0 0.5 0 1.5 25°C -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-306. ATmega1284: Power-down supply current vs. VCC (watchdog timer enabled) 11.0 85°C 10.2 9.4 ICC [µA] 8.6 -40°C 25°C 7.8 7.0 6.2 5.4 4.6 3.8 3.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 508
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.5 Power-save supply current Figure 30-307. ATmega1284: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 5.0 85°C 4.5 4.0 ICC [µA] 3.5 3.0 2.5 2.0 1.5 25°C -40°C 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.7.6 Standby supply current Figure 30-308. ATmega1284: Standby supply current vs. VCC (watchdog timer disabled) 0.25 6MHz_xtal ICC [mA] 0.20 6MHz_res 4MHz_xtal 4MHz_res 2MHz_xtal 0.
PAGE 509
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.7 Pin pull-up Figure 30-309. ATmega1284: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 35 30 IRESET [µA] 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] Figure 30-310. ATmega1284: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [µA] 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V]  2018 Microchip Technology Inc.
PAGE 510
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-311. ATmega1284: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [µA] 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 30-312. ATmega1284: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRESET [µA] 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V]  2018 Microchip Technology Inc.
PAGE 511
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-313. ATmega1284: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-314. ATmega1284: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [µA] 80 60 40 20 -40°C 25°C 85°C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VRESET [V]  2018 Microchip Technology Inc.
PAGE 512
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.8 Pin driver strength Figure 30-315. ATmega1284: I/O pin output voltage vs. sink current (VCC = 2.7V) 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -40°C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-316. ATmega1284: I/O pin output voltage vs. sink current (VCC = 3V) 0.9 85°C 0.8 0.7 25°C VOL [V] 0.6 -40°C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA]  2018 Microchip Technology Inc.
PAGE 513
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-317. ATmega1284: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-318. ATmega1284: I/O pin output voltage vs. source current (VCC = 2.7V) 3.0 VOH [V] 2.5 2.0 -40°C 25°C 1.5 85°C 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA]  2018 Microchip Technology Inc.
PAGE 514
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-319. ATmega1284: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 30.7.9 Pin threshold and hysteresis Figure 30-320. ATmega1284: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) 3.0 85°C 25°C -40°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 515
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-321. ATmega1284: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 85°C -40°C 25°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-322. ATmega1284: I/O pin input hysteresis vs. VCC 0.60 Input hysteresis [mV] 0.55 85°C 25°C -40°C 0.50 0.45 0.40 0.35 0.30 0.25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 516
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-323. ATmega1284: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-324. ATmega1284: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 -40°C 85°C 25°C Threshold (V) 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 517
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-325. ATmega1284: Reset pin input hysteresis vs. VCC 0.6 Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 -40°C 25°C 85°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.7.10 BOD threshold Figure 30-326. ATmega1284: BOD threshold vs. temperature (VBOT = 4.3V) 4.37 Rising Vcc 4.35 Threshold [V] 4.33 4.31 Falling Vcc 4.29 4.27 4.25 4.
PAGE 518
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-327. ATmega1284: BOD threshold vs. temperature (VBOT = 2.7V) 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.66 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 70 80 90 Temperature [°C] Figure 30-328. ATmega1284: BOD threshold vs. temperature (VBOT = 1.8V) 1.84 Rising Vcc 1.83 Threshold [V] 1.82 1.81 Falling Vcc 1.80 1.79 1.
PAGE 519
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-329. ATmega1284: Calibrated bandgap voltage vs. VCC 1.120 Bandgap voltage [V] 1.115 85°C 25°C 1.110 1.105 1.100 1.095 -40°C 1.090 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 30-330. ATmega1284: Bandgap voltage vs. temperature 1.120 1.8V 3.3V 5.0V 5.5V Bandgap voltage [V] 1.115 1.110 1.105 1.100 1.095 1.090 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C]  2018 Microchip Technology Inc.
PAGE 520
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.7.11 Internal oscillator speed Figure 30-331. ATmega1284: Watchdog oscillator frequency vs. temperature 123 122 121 FRC [kHz] 120 119 118 117 2.7V 116 3.3V 4.0V 5.5V 115 114 113 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-332. ATmega1284: Watchdog oscillator frequency vs. VCC 124 122 FRC [kHz] -40°C 120 25°C 118 116 85°C 114 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 521
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-333. ATmega1284: Calibrated 8MHz RC oscillator vs. VCC 8.6 85°C 8.4 25°C FRC [MHz] 8.2 8.0 -40°C 7.8 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-334. ATmega1284: Calibrated 8MHz RC oscillator vs. temperature 8.3 5.5V 8.2 3.3V 2.7V FRC [MHz] 8.1 1.8V 8.0 7.9 7.8 7.7 7.6 7.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C]  2018 Microchip Technology Inc.
PAGE 522
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-335. ATmega1284: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85°C 25°C -40°C 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] 30.7.12 Current consumption of peripheral units Figure 30-336. ATmega1284: ADC current vs. VCC (AREF = AVCC) 280 -40°C 25°C 85°C 260 240 ICC [µA] 220 200 180 160 140 120 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 523
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-337. ATmega1284: Analog comparator current vs. VCC 85 -40°C 25°C 85°C 75 ICC [µA] 65 55 45 35 25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-338. ATmega1284: AREF external reference current vs. VCC 200 85°C 25°C -40°C 180 ICC [µA] 160 140 120 100 80 60 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 524
ATmega164A/PA/324A/PA/644A/PA/1284/P ICC [µA] Figure 30-339. ATmega1284: Brownout detector current vs. VCC 25 85°C 23 25°C 21 -40°C 19 17 15 13 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-340. ATmega1284: Programming current vs. VCC 14 -40°C 12 ICC [mA] 10 25°C 8 85°C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 525
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-341. ATmega1284: Watchdog timer current vs. VCC 8.5 -40°C 7.5 25°C 85°C ICC [µA] 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.7.13 Current consumption in reset and reset pulsewidth Figure 30-342. ATmega1284: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
PAGE 526
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-343. ATmega1284: Reset supply current vs. frequency (1 - 20MHz) 1.6 5.5V 1.4 5.0V 1.2 4.5V ICC [mA] 1.0 0.8 4.0V 0.6 3.3V 0.4 2.7V 0.2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-344. ATmega1284: Minimum reset pulsewidth vs. VCC 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 400 85°C 25°C -40°C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 527
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8 ATmega1284P typical characteristics - TA = -40°C to 85°C 30.8.1 Active supply current ICC [mA] Figure 30-345. ATmega1284P: Active supply current vs. low frequency (0.1 - 1.0MHz) 1.6 5.5V 1.4 5.0V 1.2 4.5V 1.0 4.0V 0.8 3.3V 0.6 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-346. ATmega1284P: Active supply current vs. frequency (1 - 20MHz) 20 5.5V 18 5.0V 16 4.5V ICC [mA] 14 12 4.
PAGE 528
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-347. ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 8MHz) 9 85°C 25°C -40°C 8 7 ICC [mA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-348. ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 1MHz) 1.8 85°C 25°C -40°C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 529
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-349. ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 128kHz) 0.28 -40°C 25°C 85°C 0.24 ICC [mA] 0.20 0.16 0.12 0.08 0.04 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.8.2 Idle supply current Figure 30-350. ATmega1284P: Idle supply current vs. low frequency (0.1 - 1.0MHz) 0.24 5.5V 0.21 5.0V 0.18 4.5V 4.0V 3.6V ICC [mA] 0.15 0.12 2.7V 0.09 1.8V 0.06 0.03 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
PAGE 530
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-351. ATmega1284P: Idle supply current vs. frequency (1 - 20MHz) 3.0 5.5V 2.5 5.0V 4.5V ICC [mA] 2.0 1.5 4.0V 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-352. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 8MHz) 1.4 85°C 1.2 25°C -40°C ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 531
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-353. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 1MHz) 0.42 85°C 25°C -40°C 0.36 ICC [mA] 0.30 0.24 0.18 0.12 0.06 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-354. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 128kHz) 0.12 -40°C 85°C 25°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 532
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 56 for details. Table 30-15.
PAGE 533
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.4 Power-down supply current Figure 30-355. ATmega1284P: Power-down supply current vs. VCC (watchdog timer disabled) 4.0 85°C 3.5 3.0 ICC [µA] 2.5 2.0 1.5 1.0 0.5 0 1.5 25°C -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-356. ATmega1284P: Power-down supply current vs. VCC (watchdog timer enabled) 11.0 85°C 10.2 9.4 ICC [µA] 8.6 -40°C 25°C 7.8 7.0 6.2 5.4 4.6 3.8 3.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 534
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.5 Power-save supply current Figure 30-357. ATmega1284P: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) 5.0 85°C 4.5 4.0 ICC [µA] 3.5 3.0 2.5 2.0 1.5 25°C -40°C 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.8.6 Standby supply current Figure 30-358. ATmega1284P: Standby supply current vs. VCC (watchdog timer disabled) 0.25 6MHz_xtal ICC [mA] 0.20 6MHz_res 4MHz_xtal 4MHz_res 2MHz_xtal 0.
PAGE 535
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.7 Pin pull-up Figure 30-359. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) 35 30 IRESET [µA] 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] Figure 30-360. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) 80 70 60 IOP [µA] 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOP [V]  2018 Microchip Technology Inc.
PAGE 536
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-361. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) 140 120 IOP [µA] 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 30-362. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 35 30 IRESET [µA] 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V]  2018 Microchip Technology Inc.
PAGE 537
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-363. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 30-364. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) 120 100 IRESET [µA] 80 60 40 20 -40°C 25°C 85°C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VRESET [V]  2018 Microchip Technology Inc.
PAGE 538
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.8 Pin driver strength Figure 30-365. ATmega1284P: I/O pin output voltage vs. sink current (VCC = 2.7V) 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -40°C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-366. ATmega1284P: I/O pin output voltage vs. sink current (VCC = 3V) 0.9 85°C 0.8 0.7 25°C VOL [V] 0.6 -40°C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA]  2018 Microchip Technology Inc.
PAGE 539
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-367. ATmega1284P: I/O pin output voltage vs. sink current (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-368. ATmega1284P: I/O pin output voltage vs. source current (VCC = 2.7V) 3.0 VOH [V] 2.5 2.0 -40°C 25°C 1.5 85°C 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA]  2018 Microchip Technology Inc.
PAGE 540
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-369. ATmega1284P: I/O pin output voltage vs. source current (VCC = 3V) 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 30.8.9 Pin threshold and hysteresis Figure 30-370. ATmega1284P: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) 3.0 85°C 25°C -40°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 541
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-371. ATmega1284P: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 85°C -40°C 25°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-372. ATmega1284P: I/O pin input hysteresis vs. VCC 0.60 Input hysteresis [mV] 0.55 85°C 25°C -40°C 0.50 0.45 0.40 0.35 0.30 0.25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 542
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-373. ATmega1284P: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-374. ATmega1284P: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) 2.5 -40°C 85°C 25°C Threshold (V) 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 543
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-375. ATmega1284P: Reset pin input hysteresis vs. VCC 0.6 Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 -40°C 25°C 85°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.8.10 BOD threshold Figure 30-376. ATmega1284P: BOD threshold vs. temperature (VBOT = 4.3V) 4.37 Rising Vcc 4.35 Threshold [V] 4.33 4.31 Falling Vcc 4.29 4.27 4.25 4.
PAGE 544
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-377. ATmega1284P: BOD threshold vs. temperature (VBOT = 2.7V) 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.66 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 80 90 Temperature [°C] Figure 30-378. ATmega1284P: BOD threshold vs. temperature (VBOT = 1.8V) 1.84 Rising Vcc 1.83 Threshold [V] 1.82 1.81 Falling Vcc 1.80 1.79 1.
PAGE 545
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-379. ATmega1284P: Calibrated bandgap voltage vs. VCC 1.120 Bandgap voltage [V] 1.115 85°C 25°C 1.110 1.105 1.100 1.095 -40°C 1.090 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 30-380. ATmega1284P: Bandgap voltage vs. temperature 1.120 1.8V 3.3V 5.0V 5.5V Bandgap voltage [V] 1.115 1.110 1.105 1.100 1.095 1.090 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C]  2018 Microchip Technology Inc.
PAGE 546
ATmega164A/PA/324A/PA/644A/PA/1284/P 30.8.11 Internal oscillator speed Figure 30-381. ATmega1284P: Watchdog oscillator frequency vs. temperature 123 122 121 FRC [kHz] 120 119 118 117 2.7V 116 3.3V 4.0V 5.5V 115 114 113 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-382. ATmega1284P: Watchdog oscillator frequency vs. VCC 124 122 FRC [kHz] -40°C 120 25°C 118 116 85°C 114 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 547
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-383. ATmega1284P: Calibrated 8MHz RC oscillator vs. VCC 8.6 85°C 8.4 25°C FRC [MHz] 8.2 8.0 -40°C 7.8 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-384. ATmega1284P: Calibrated 8MHz RC oscillator vs. temperature 8.3 5.5V 8.2 3.3V 2.7V FRC [MHz] 8.1 1.8V 8.0 7.9 7.8 7.7 7.6 7.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C]  2018 Microchip Technology Inc.
PAGE 548
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-385. ATmega1284P: Calibrated 8MHz RC oscillator vs. OSCCAL value 16 85°C 25°C -40°C 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] 30.8.12 Current consumption of peripheral units Figure 30-386. ATmega1284P: ADC current vs. VCC (AREF = AVCC) 280 -40°C 25°C 85°C 260 240 ICC [µA] 220 200 180 160 140 120 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 549
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-387. ATmega1284P: Analog comparator current vs. VCC 85 -40°C 25°C 85°C 75 ICC [µA] 65 55 45 35 25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-388. ATmega1284P: AREF external reference current vs. VCC 200 85°C 25°C -40°C 180 ICC [µA] 160 140 120 100 80 60 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 550
ATmega164A/PA/324A/PA/644A/PA/1284/P ICC [µA] Figure 30-389. ATmega1284P: Brownout detector current vs. VCC 25 85°C 23 25°C 21 -40°C 19 17 15 13 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-390. ATmega1284P: Programming current vs. VCC 14 -40°C 12 ICC [mA] 10 25°C 8 85°C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 551
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-391. ATmega1284P: Watchdog timer current vs. VCC 8.5 -40°C 7.5 25°C 85°C ICC [µA] 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.8.13 Current consumption in reset and reset pulsewidth Figure 30-392. ATmega1284P: Reset supply current vs. low frequency (0.1 - 1.0MHz) 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
PAGE 552
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 30-393. ATmega1284P: Reset supply current vs. frequency (1 - 20MHz) 1.6 5.5V 1.4 5.0V 1.2 4.5V ICC [mA] 1.0 0.8 4.0V 0.6 3.3V 0.4 2.7V 0.2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-394. ATmega1284P: Minimum reset pulsewidth vs. VCC 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 400 85°C 25°C -40°C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V]  2018 Microchip Technology Inc.
PAGE 553
ATmega164A/PA/324A/PA/644A/PA/1284/P 31. Typical Characteristics - TA = -40°C to 105°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source.
PAGE 554
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1 ATmega164PA Typical Characteristics - TA = -40°C to 105°C 31.1.1 Active supply current Figure 31-1. ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 8MHz) >&@ ,&& >P$@ 9&& >9@ Figure 31-2. ATmega164PA: Active supply current vs.
PAGE 555
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-3. ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 128kHz) >&@ ,&& >P$@ 9&& >9@ 31.1.2 Idle supply current Figure 31-4. ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 8MHz) >&@ ,&& >P$@  2018 Microchip Technology Inc.
PAGE 556
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-5. ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 1MHz) >&@ ,&& >P$@ Figure 31-6. 9&& >9@ ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 128kHz) >&@ ,&&>P$@ 9&& >9@  2018 Microchip Technology Inc.
PAGE 557
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.3 Power-down supply current Figure 31-7. ATmega164PA: Power-down supply current vs. VCC (watchdog timer disabled) >&@ ,&& >X$@ Figure 31-8. 9&& >9@ ATmega164PA: Power-down supply current vs. VCC (watchdog timer enabled) ,&& >X$@ >&@ 9&& >9@  2018 Microchip Technology Inc.
PAGE 558
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.4 Pin pull-up Figure 31-9. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V) >&@ ,23 >X$@ 923 >9@ Figure 31-10. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) >&@ ,23 >X$@ 923 >9@  2018 Microchip Technology Inc.
PAGE 559
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-11. ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) >&@ ,23 >X$@ 923 >9@ Figure 31-12. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) 9FF 9 >&@ ,5( 6 (7 >X$@  2018 Microchip Technology Inc.
PAGE 560
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-13. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V) >&@ ,5( 6 (7 >X$@ 95( 6 (7 >9@ Figure 31-14. ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) >&@ ,5( 6 (7 >X$@ 95( 6 (7 >9@  2018 Microchip Technology Inc.
PAGE 561
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.5 Pin driver strength Figure 31-15. ATmega164PA: I/O pin output voltage vs. sink current (VCC = 3V) >&@ 92/ >9@ ,2/ >P$@ Figure 31-16. ATmega164PA: I/O pin output voltage vs. sink current (VCC = 5V) 92/ >9@  2018 Microchip Technology Inc.
PAGE 562
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-17. ATmega164PA: I/O pin output voltage vs. source current (VCC = 3V) >&@ 92+ >9@ ,2+ >P$@ Figure 31-18. ATmega164PA: I/O pin output voltage vs. source current (VCC = 5V) 92+ >9@ >&@  2018 Microchip Technology Inc.
PAGE 563
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.6 Pin threshold and hysteresis Figure 31-19. ATmega164PA: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) >&@ 7KUHVKROG >9@ 9&& >9@ Figure 31-20. ATmega164PA: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) >&@ 7KUHVKROG >9@  2018 Microchip Technology Inc.
PAGE 564
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-21. ATmega164PA: I/O pin input hysteresis vs. VCC ,QSXW +\VWHUHVLV >P9@ >&@ 9&& >9@ Figure 31-22. ATmega164PA: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) >&@ 7KUHVKROG >9@  2018 Microchip Technology Inc.
PAGE 565
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-23. ATmega164PA: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) >&@ 7KUHVKROG >9@ 9&& >9@ Figure 31-24. ATmega164PA: Reset pin input hysteresis vs. VCC >&@ ,QSXW +\VWHUHVLV >P9@  2018 Microchip Technology Inc.
PAGE 566
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.7 BOD threshold Figure 31-25. ATmega164PA: BOD threshold vs. temperature (VBOT = 4.3V) 7KUHVKROG >9@ 5LVLQJ 9FF )DOOLQJ 9FF 7HPSHUDWXUH >&@ Figure 31-26. ATmega164PA: BOD threshold vs. temperature (VBOT = 2.7V) 7KUHVKROG >9 5LVLQJ 9FF )DOOLQJ 9FF  2018 Microchip Technology Inc.
PAGE 567
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-27. ATmega164PA: BOD threshold vs. temperature (VBOT = 1.8V) 7KUHVKROG >9@ 5LVLQJ 9FF )DOOLQJ 9FF 7HPSHUDWXUH >&@ Figure 31-28. ATmega164PA: Calibrated bandgap voltage vs.
PAGE 568
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-29. ATmega164PA: Bandgap voltage vs. temperature >9@ %DQGJDS 9ROWDJH 9 7HPSHUDWXUH >&@ 31.1.8 Internal oscillator speed Figure 31-30. ATmega164PA: Watchdog oscillator frequency vs. temperature >9@ )5& N+]@  2018 Microchip Technology Inc.
PAGE 569
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-31. ATmega164PA: Watchdog oscillator frequency vs. VCC >&@ )5& >N+]@ 9&& >9@ Figure 31-32. ATmega164PA: Calibrated 8MHz RC oscillator vs. VCC >&@ )5& >0+]@  2018 Microchip Technology Inc.
PAGE 570
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-33. ATmega164PA: Calibrated 8MHz RC oscillator vs. temperature 9 9 )5& >0+]@ 7HPSHUDWXUH >&@ Figure 31-34. ATmega164PA: Calibrated 8MHz RC oscillator vs. OSCCAL value >&@ )5& >0+]@ 26& &$/ >; @  2018 Microchip Technology Inc.
PAGE 571
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.9 Current consumption of peripheral units Figure 31-35. ATmega164PA: ADC current vs. VCC (AREF = AVCC) ,&& >X$@ 9&& >9@ Figure 31-36. ATmega164PA: Analog comparator current vs. VCC >&@ ,&& >X$@  2018 Microchip Technology Inc.
PAGE 572
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-37. ATmega164PA: AREF external reference current vs. VCC >&@ ,&& >X$@ 9&& >9@ Figure 31-38. ATmega164PA: Brownout detector current vs. VCC >&@ ,&& >X$@  2018 Microchip Technology Inc.
PAGE 573
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-39. ATmega164PA: Programming current vs. VCC >&@ ,&& >P$@ 9&& >9@ Figure 31-40. ATmega164PA: Watchdog timer current vs. VCC ,&& >X$@  2018 Microchip Technology Inc.
PAGE 574
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.1.10 Current consumption in reset and reset pulsewidth Figure 31-41. ATmega164PA: Minimum reset pulsewidth vs. VCC 3XOVHZLGWK >QV@ 9&& >9@ 31.2.1 ATmega324PA Typical Characteristics - TA = -40°C to 105°C Active Supply Current Figure 31-42. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 7 105 °C 85 °C 25 °C -40 °C 6 5 ICC (mA) 31.2 4 3 2 1 0 1.5 2 2.
PAGE 575
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-43. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 1.6 105 °C 85 °C 25 °C -40 °C 1.4 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-44. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.25 -40 °C 25 °C 105 °C 85 °C ICC (mA) 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 576
ATmega164A/PA/324A/PA/644A/PA/1284/P Idle Supply Current Figure 31-45. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 1.8 105 °C 85 °C 25 °C -40 °C 1.6 1.4 ICC (mA) 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-46. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 0.7 105 °C 85 °C 25 °C -40 °C 0.6 0.5 ICC (mA) 31.2.2 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 577
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-47. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.12 -40 °C 105 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 31-48. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 3 105 °C 2.5 2 ICC (uA) 31.2.3 1.5 85 °C 1 0.5 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 578
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-49. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 10 105 °C -40 °C 85 °C 25 °C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-up Figure 31-50. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 35 IOP (uA) 31.2.4 30 25 20 15 25 °C 85 °C -40 °C 105 °C 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V)  2018 Microchip Technology Inc.
PAGE 579
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-51. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 25 °C 85 °C 105 °C -40 °C 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 31-52. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C 105 °C -40 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V)  2018 Microchip Technology Inc.
PAGE 580
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-53. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRESET (uA) 25 20 15 10 -40 °C 25 °C 85 °C 105 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET (V) Figure 31-54. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 105 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V)  2018 Microchip Technology Inc.
PAGE 581
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-55. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET (uA) 80 60 40 25 °C -40 °C 85 °C 105 °C 20 0 0 1 2 3 4 5 VRESET (V) Pin Driver Strength Figure 31-56. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 1 105 °C 0.9 85 °C 0.8 0.7 VOL (V) 31.2.5 25 °C 0.6 -40 °C 0.5 0.4 0.3 0.2 0.1 0 0 4 8 12 16 20 Load current (mA)  2018 Microchip Technology Inc.
PAGE 582
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-57. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 105 °C 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.1 0 0 4 8 12 16 20 Load current (mA) Figure 31-58. I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 105 °C 2 1.5 1 0.5 0 0 4 8 12 16 20 Load current (mA)  2018 Microchip Technology Inc.
PAGE 583
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-59. I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5 4.9 VOH (V) 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 105 °C 4.3 0 4 8 12 16 20 Load current (mA) Pin Threshold and Hysteresis Figure 31-60. I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 3 -40 °C 25 °C 85 °C 105 °C 2.5 Threshold (V) 31.2.6 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 584
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-61. I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 2.5 105 °C 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-62. I/O Pin Input Hysteresis vs. VCC 0.6 -40 °C 25 °C 85 °C 105 °C Input Hysteresis (mV) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 585
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-63. Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 2.5 -40 °C 25 °C 85 °C 105 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-64. Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 2.5 105 °C 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 586
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-65. Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 105 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 90 100 110 VCC (V) BOD Threshold Figure 31-66. BOD Threshold vs. Temperature (VCC = 4.3V) 4.4 Rising Vcc 4.38 Threshold (V) 31.2.7 4.36 4.34 4.32 Falling Vcc 4.3 4.28 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C)  2018 Microchip Technology Inc.
PAGE 587
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-67. BOD Threshold vs. Temperature (VCC = 2.7V) 2.79 Rising Vcc Threshold (V) 2.77 2.75 2.73 2.71 Falling Vcc 2.69 2.67 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 60 70 80 90 100 110 Temperature (°C) Figure 31-68. BOD Threshold vs. Temperature (VCC = 1.8V) 1.85 Rising Vcc 1.84 Threshold (V) 1.83 1.82 Falling Vcc 1.81 1.8 1.79 1.
PAGE 588
ATmega164A/PA/324A/PA/644A/PA/1284/P Internal Oscillator Speed Figure 31-69. Watchdog Oscillator Frequency vs. Temperature 122 120 FRC (kHz) 118 116 114 1.8 V 2.7 V 3.3 V 4.0 V 5.5 V 112 110 108 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 31-70. Watchdog Oscillator Frequency vs. VCC 122 FRC (kHz) 31.2.8 120 -40 °C 118 25 °C 116 114 85 °C 112 105 °C 110 108 106 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 589
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-71. Calibrated 8 MHz RC Oscillator vs. VCC 8.6 105 °C 85 °C 8.4 FRC (MHz) 8.2 25 °C 8 7.8 7.6 -40 °C 7.4 7.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-72. Calibrated 8 MHz RC Oscillator vs. Temperature 8.6 5.0 V 3.0 V 8.4 FRC (MHz) 8.2 8 7.8 7.6 7.4 7.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C)  2018 Microchip Technology Inc.
PAGE 590
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-73. Calibrated 8 MHz RC Oscillator vs. OSCCAL Value 14 105 °C 85 °C 25 °C -40 °C 12 FRC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Current Consumption of Peripheral Units Figure 31-74. ADC Current vs. VCC (AREF = AVCC) 300 25 °C -40 °C 85 °C 105 °C 250 200 ICC (uA) 31.2.9 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 591
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-75. Analog Comparator Current vs. VCC 90 -40 °C 25 °C 105 °C 85 °C 80 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-76. AREF External Reference Current vs. VCC 200 25 °C 105 °C 85 °C -40 °C ICC (uA) 160 120 80 40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 592
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-77. Brownout Detector Current vs. VCC 30 105 °C 85 °C 25 °C -40 °C 25 ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-78. Programming Current vs. VCC 14 25 °C -40 °C 85 °C 105 °C 12 ICC (mA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 593
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-79. Watchdog Timer Current vs. VCC 9 -40 °C 25 °C 85 °C 105 °C 8 7 ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Current Consumption in Reset and Reset Pulsewidth Figure 31-80. Minimum Reset Pulsewidth vs. Vcc 1800 1500 Pulsewidth (ns) 31.2.10 1200 900 600 105 °C 85 °C 25 °C -40 °C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 594
ATmega164A/PA/324A/PA/644A/PA/1284/P Active Supply Current Figure 31-81. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 7 105 °C 85 °C 25 °C -40 °C 6 5 ICC (mA) 31.3.1 ATmega644PA Typical Characteristics - TA = -40°C to 105°C 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-82. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 1.4 105 °C 85 °C 25 °C -40 °C 1.2 1 ICC (mA) 31.3 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 595
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-83. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.24 -40 °C 25 °C 105 °C 85 °C 0.21 0.18 ICC (mA) 0.15 0.12 0.09 0.06 0.03 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 31-84. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 1.4 105 °C 85 °C 25 °C -40 °C 1.2 1 ICC (mA) 31.3.2 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 596
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-85. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 105 °C 85 °C 25 °C -40 °C 0.36 0.3 ICC (mA) 0.24 0.18 0.12 0.06 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-86. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 105 °C 85 °C 25 °C -40 °C 0.36 0.3 ICC (mA) 0.24 0.18 0.12 0.06 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 597
ATmega164A/PA/324A/PA/644A/PA/1284/P Power-down Supply Current Figure 31-87. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 6 105 °C 5 ICC (uA) 4 3 85 °C 2 1 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-88. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 14 105 °C 12 10 ICC (uA) 31.3.3 85 °C -40 °C 25 °C 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 598
ATmega164A/PA/324A/PA/644A/PA/1284/P Pin Pull-up Figure 31-89. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 IOP (uA) 40 30 20 10 25 °C 85 °C -40 °C 105 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 31-90. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 50 IOP (uA) 31.3.4 40 30 20 25 °C 85 °C -40 °C 105 °C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VOP (V)  2018 Microchip Technology Inc.
PAGE 599
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-91. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C -40 °C 105 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 31-92. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRESET (uA) 25 20 15 10 25 °C -40 °C 85 °C 105 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET (V)  2018 Microchip Technology Inc.
PAGE 600
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-93. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 105 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 31-94. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 110 100 90 80 IRESET (uA) 70 60 50 40 30 25 °C -40 °C 85 °C 105 °C 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V)  2018 Microchip Technology Inc.
PAGE 601
ATmega164A/PA/324A/PA/644A/PA/1284/P Pin Driver Strength Figure 31-95. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 1 105 °C 85 °C 0.9 0.8 0.7 25 °C VOL (V) 0.6 -40 °C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 Load current (mA) Figure 31-96. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 105 °C 85 °C 0.5 25 °C 0.4 VOL (V) 31.3.5 -40 °C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 Load current (mA)  2018 Microchip Technology Inc.
PAGE 602
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-97. I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.1 2.9 VOH (V) 2.7 2.5 -40 °C 2.3 25 °C 2.1 85 °C 105 °C 1.9 1.7 0 2 4 6 8 10 12 14 16 18 20 Load current (mA) Figure 31-98. I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5.1 5 VOH (V) 4.9 4.8 4.7 4.6 -40 °C 4.5 25 °C 85 °C 105 °C 4.4 4.3 0 2 4 6 8 10 12 14 16 18 20 Load current (mA)  2018 Microchip Technology Inc.
PAGE 603
ATmega164A/PA/324A/PA/644A/PA/1284/P Pin Threshold and Hysteresis Figure 31-99. I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 105 °C 85 °C 25 °C -40 °C 3 2.7 Threshold (V) 2.4 2.1 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-100. I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 2.5 105 °C 85 °C 25 °C -40 °C 2 Threshold (V) 31.3.6 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 604
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-101. I/O Pin Input Hysteresis vs. VCC 0.6 -40 °C 25 °C 85 °C 105 °C Input Hysteresis (mV) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-102. Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 2.4 -40 °C 25 °C 85 °C 105 °C 2.1 Threshold (V) 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 605
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-103. Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 2.4 105 °C 85 °C 25 °C -40 °C 2.1 Threshold (V) 1.8 1.5 1.2 0.9 0.6 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-104. Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 105 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 606
ATmega164A/PA/324A/PA/644A/PA/1284/P BOD Threshold Figure 31-105. BOD Threshold vs. Temperature (VCC = 4.3V) 4.37 Rising Vcc 4.35 Threshold (V) 4.33 4.31 4.29 Falling Vcc 4.27 4.25 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 31-106. BOD Threshold vs. Temperature (VCC = 2.7V) 2.775 Rising Vcc 2.755 2.735 Threshold (V) 31.3.7 2.715 Falling Vcc 2.695 2.675 2.
PAGE 607
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-107. BOD Threshold vs. Temperature (VCC = 1.8V) 1.825 Rising Vcc Threshold (V) 1.815 1.805 1.795 Falling Vcc 1.785 1.775 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Internal Oscillator Speed Figure 31-108. Watchdog Oscillator Frequency vs. Temperature 120 118 116 FRC (kHz) 31.3.8 114 112 2.1 V 110 3.3 V 4.5 V 5.
PAGE 608
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-109. Watchdog Oscillator Frequency vs. VCC 120 FRC (kHz) 118 116 -40 °C 114 25 °C 112 110 85 °C 108 105 °C 106 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-110. Calibrated 8 MHz RC Oscillator vs. VCC 8.4 105 °C 85 °C 8.3 8.2 25 °C FRC (MHz) 8.1 8 7.9 -40 °C 7.8 7.7 7.6 7.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 609
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-111. Calibrated 8 MHz RC Oscillator vs. Temperature 8.4 5.5 V 4.5 V 3.6 V 2.7 V 8.3 8.2 FRC (MHz) 8.1 1.8 V 8 7.9 7.8 7.7 7.6 7.5 7.4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 31-112. Calibrated 8 MHz RC Oscillator vs. OSCCAL Value 16 105 °C 85 °C 25 °C -40 °C 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1)  2018 Microchip Technology Inc.
PAGE 610
ATmega164A/PA/324A/PA/644A/PA/1284/P Current Consumption of Peripheral Units Figure 31-113. ADC Current vs. VCC (AREF = AVCC) 250 105 °C 85 °C 25 °C -40 °C 225 ICC (uA) 200 175 150 125 100 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-114. Analog Comparator Current vs. VCC 90 -40 °C 80 25 °C 85 °C 105 °C 70 ICC (uA) 31.3.9 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 611
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-115. AREF External Reference Current vs. VCC 200 105 °C 85 °C 25 °C -40 °C 175 150 ICC (uA) 125 100 75 50 25 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-116. Brownout Detector Current vs. VCC 25 105 °C 85 °C 25 °C -40 °C ICC (uA) 22 19 16 13 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 612
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-117. Programming Current vs. VCC -40 °C 16 14 12 ICC (mA) 10 25 °C 8 85 °C 105 °C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-118. Watchdog Timer Current vs. VCC 8 -40 °C 25 °C 85 °C 105 °C 7 6 ICC (uA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V)  2018 Microchip Technology Inc.
PAGE 613
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.3.10 Current Consumption in Reset and Reset Pulsewidth Figure 31-119. Minimum Reset Pulsewidth vs. Vcc 1800 1600 Pulsewidth (ns) 1400 1200 1000 800 600 105 °C 85 °C 25 °C -40 °C 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 31.4 ATmega1284P typical characteristics - TA = -40°C to 105°C 31.4.1 Active supply current Figure 31-120. ATmega1284P: Active supply current vs.
PAGE 614
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-121. ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 1MHz) > &@ ,&& >P$@ 9&& >9@ . Figure 31-122. ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 128kHz) > &@ ,&& >P$@ & 9&& >9@ .  2018 Microchip Technology Inc.
PAGE 615
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.4.2 Idle supply current Figure 31-123. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 8MHz) & & & & ,&& >P$@ 9&& >9@ Figure 31-124. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 1MHz) ,&& >P$@ > &@ 9&& >9@  2018 Microchip Technology Inc.
PAGE 616
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-125. ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 128kHz) > &@ ,&& >P$@ 9&& >9@  2018 Microchip Technology Inc.
PAGE 617
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.4.3 Power-down supply current Figure 31-126. ATmega1284P: Power-down supply current vs. VCC (watchdog timer disabled) & ,&& >X$@ & & & 9&& >9@ Figure 31-127. ATmega1284P: Power-down supply current vs. VCC (watchdog timer enabled) ,&& >X$@ > &@ 9&& >9@  2018 Microchip Technology Inc.
PAGE 618
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.4.4 Power-save supply current Figure 31-128. ATmega1284P: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running) * DD <"> >&@ 7DD <7> 31.4.5 Pin pull-up Figure 31-129. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 1.
PAGE 619
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-130. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V) ,23 >X$@ > &@ 923 >9@ Figure 31-131. ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 5V) ,23 >X$` > &@ 923 >9@  2018 Microchip Technology Inc.
PAGE 620
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-132. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V) ,5( 6 (7 >X$@ > &@ 95(6( 7 >9@ Figure 31-133. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.
PAGE 621
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-134. ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V) ,5( 6 (7 >X$@ > &@ 95(6( 7 >9@  2018 Microchip Technology Inc.
PAGE 622
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.4.6 Pin driver strength Figure 31-135. ATmega1284P: I/O pin output voltage vs. sink current (VCC = 2.7V) 92/ >9@ > &@ , 2/ >P$@ Figure 31-136. ATmega1284P: I/O pin output voltage vs.
PAGE 623
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-137. ATmega1284P: I/O pin output voltage vs. sink current (VCC = 5V) >&@ 92/ >9@ , 2/ >P$@ Figure 31-138. ATmega1284P: I/O pin output voltage (VOH) vs. source current (VCC = 2.7V) 92+ >9@ >&@ , 2+ >P$@  2018 Microchip Technology Inc.
PAGE 624
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-139. ATmega1284P: I/O pin output voltage vs. source current (VCC = 3V) 92+ >9@ >&@ , 2+ >P$@ 31.4.7 Pin threshold and hysteresis Figure 31-140. ATmega1284P: I/O pin input threshold vs.
PAGE 625
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-141. ATmega1284P: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’) > &@ 7KUHVKROG >9@ 9&& >9@ Figure 31-142. ATmega1284P: I/O pin input hysteresis vs. VCC ,QSXW +\VWHUHVLV P9 > &@ 9&& >9@  2018 Microchip Technology Inc.
PAGE 626
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-143. ATmega1284P: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’) 7KUHVKROG >9@ >&@ 9&& >9@ Figure 31-144. ATmega1284P: Reset pin input threshold vs.
PAGE 627
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-145. ATmega1284P: Reset pin input hysteresis vs. VCC ,QSXW +\VWHUHVLV >P9@ > &@ 9&& >9@ 31.4.8 BOD threshold Figure 31-146. ATmega1284P: BOD threshold vs. temperature (VBOT = 4.
PAGE 628
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-147. ATmega1284P: BOD threshold vs. temperature (VBOT = 2.7V) 7KUHVKROG >9@ 5LVLQJ 9FF )DOOLQJ 9FF 7HPSHUDWXUH >&@ Figure 31-148. ATmega1284P: BOD threshold vs. temperature (VBOT = 1.
PAGE 629
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-149. ATmega1284P: Calibrated bandgap voltage vs. VCC %DQGJDS 9ROWDJH >9@ > &@ 9FF >9@ Figure 31-150. ATmega1284P: Bandgap voltage vs. temperature %DQGJDS 9ROWDJH >9@ >9@ 7HPSHUDWXUH >&@  2018 Microchip Technology Inc.
PAGE 630
ATmega164A/PA/324A/PA/644A/PA/1284/P 31.4.9 Internal oscillator speed Figure 31-151. ATmega1284P: Watchdog oscillator frequency vs. temperature )5& >N+]@ >9@ 7HPSHUDWXUH >&@ Figure 31-152. ATmega1284P: Watchdog oscillator frequency vs.
PAGE 631
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-153. ATmega1284P: Calibrated 8MHz RC oscillator vs. VCC >&@ )5& >0+]@ 9&& >9@ Figure 31-154. ATmega1284P: Calibrated 8MHz RC oscillator vs. temperature )5& >0+]@ >9@ 7HPSHUDWXUH >&@  2018 Microchip Technology Inc.
PAGE 632
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-155. ATmega1284P: Calibrated 8MHz RC oscillator vs. OSCCAL value ) 5&>0+]@ >&@ 26& &$/ >; @ 31.4.10 Current consumption of peripheral units Figure 31-156. ATmega1284P: ADC current vs.
PAGE 633
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-157. ATmega1284P: Analog comparator current vs. VCC >&@ ,&& > X$@ 9&& >9@ Figure 31-158. ATmega1284P: AREF external reference current vs. VCC >&@ ,&& >X$@ 9&& >9@  2018 Microchip Technology Inc.
PAGE 634
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-159. ATmega1284P: Brownout detector current vs. VCC ,&& >X$@ >&@ 9&& >9@ Figure 31-160. ATmega1284P: Programming current vs. VCC ,&& >P$@ >&@  2018 Microchip Technology Inc.
PAGE 635
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 31-161. ATmega1284P: Watchdog timer current vs. VCC ,&& >X$@ 9&& >9@ 31.4.11 Current consumption in reset and reset pulsewidth Figure 31-162. ATmega1284P: Minimum reset pulsewidth vs. VCC 3XOVHZLGWK >QV@ >&@ 9&& >9@  2018 Microchip Technology Inc.
PAGE 636
ATmega164A/PA/324A/PA/644A/PA/1284/P 32.
PAGE 637
ATmega164A/PA/324A/PA/644A/PA/1284/P Address (0xC0) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page UCSR0A Name RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 193/208 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - 239 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE 236 (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 two-wire Serial Interface Data Register TWA2 TWA1
PAGE 638
ATmega164A/PA/324A/PA/644A/PA/1284/P Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7C) ADMUX Name REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Page 257 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 241 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 258 (0x79) ADCH ADC Data Register High byte (0x78) ADCL ADC Data Register Low byte (0x77) Reserved - - - - - - - - (0x76) Reserved - - - - - - - - (0x75) Reserved - - -
PAGE 639
ATmega164A/PA/324A/PA/644A/PA/1284/P Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x18 (0x38) Address TIFR3 Name - - ICF3 - - OCF3B OCF3A TOV3 144 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 164 0x16 (0x36) TIFR1 - - ICF1 - - OCF1B OCF1A TOV1 143 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 114 0x14 (0x34) Reserved - - - - - - - - 0x13 (0x33) Reserved - - - - - - - - 0x12 (0x32) Reserved - - - - - - - - 0x11 (0x31)
PAGE 640
ATmega164A/PA/324A/PA/644A/PA/1284/P 33.
PAGE 641
ATmega164A/PA/324A/PA/644A/PA/1284/P Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC  PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC  PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC  PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b)  1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b)  0 None 2 LSL Rd L
PAGE 642
ATmega164A/PA/324A/PA/644A/PA/1284/P Mnemonics Operands Description Operation Flags #Clocks MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/timer) For On-chip Debug Only None None 1 N/A  2018 Microchip Technology Inc.
PAGE 643
ATmega164A/PA/324A/PA/644A/PA/1284/P 34. Ordering information 34.1 ATmega164A Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code(2) ATmega164A-AU ATmega164A-AUR(5) ATmega164A-PU ATmega164A-MU ATmega164A-MUR(5) ATmega164A-MCH(4) ATmega164A-MCHR(4)(5) ATmega164A-CU ATmega164A-CUR(5) Package(1) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form.
PAGE 644
ATmega164A/PA/324A/PA/644A/PA/1284/P 34.2 ATmega164PA Speed [MHz] (3) 20 20 Notes: Power supply Ordering code (2) Package (1) Operational range 1.8 - 5.5V ATmega164PA-AU ATmega164PA-AUR(5) ATmega164PA-PU ATmega164PA-MU ATmega164PA-MUR(5) ATmega164PA-MCH(4) ATmega164PA-MCHR(4)(5) ATmega164PA-CU ATmega164PA-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Industrial (-40oC to 85oC) 1.8 - 5.
PAGE 645
ATmega164A/PA/324A/PA/644A/PA/1284/P 34.3 ATmega324A Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) ATmega324A-AU ATmega324A-AUR(5) ATmega324A-PU ATmega324A-MU ATmega324A-MUR(5) ATmega324A-MCH(4) ATmega324A-MCHR(4)(5) ATmega324A-CU ATmega324A-CUR(5) Package (1) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form.
PAGE 646
ATmega164A/PA/324A/PA/644A/PA/1284/P 34.4 ATmega324PA Speed [MHz] (3) 20 20 Notes: Power supply Ordering code (2) Package (1) Operational range 1.8 - 5.5V ATmega324PA-AU ATmega324PA-AUR(5) ATmega324PA-PU ATmega324PA-MU ATmega324PA-MUR(5) ATmega324PA-MCH(4) ATmega324PA-MCHR(4)(5) ATmega324PA-CU ATmega324PA-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Industrial (-40oC to 85oC) 1.8 - 5.
PAGE 647
ATmega164A/PA/324A/PA/644A/PA/1284/P 34.5 ATmega644A Speed [MHz](3) 20 Notes: Power supply 1.8 - 5.5V Ordering code(2) ATmega644A-AU ATmega644A-AUR(4) ATmega644A-PU ATmega644A-MU ATmega644A-MUR(4) Package(1) 44A 44A 40P6 44M1 44M1 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering information and minimum quantities. 2.
PAGE 648
ATmega164A/PA/324A/PA/644A/PA/1284/P 34.6 ATmega644PA Speed [MHz] (3) 20 20 Notes: Power supply Ordering code (2) Package (1) 1.8 - 5.5V ATmega644PA-AU ATmega644PA-AUR(4) ATmega644PA-PU ATmega644PA-MU ATmega644PA-MUR(4) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 85oC) 1.8 - 5.5V ATmega644PA-AN ATmega644PA-ANR(4) ATmega644PA-PN ATmega644PA-MN ATmega644PA-MNR(4) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 105oC) Operational range 1. This device can also be supplied in wafer form.
PAGE 649
ATmega164A/PA/324A/PA/644A/PA/1284/P 34.7 ATmega1284 Speed [MHz](3) 20 Notes: Power supply 1.8 - 5.5V Ordering code(2) ATmega1284-AU ATmega1284-AUR(4) ATmega1284-PU ATmega1284-MU ATmega1284-MUR(4) Package(1) 44A 44A 40P6 44M1 44M1 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering information and minimum quantities. 2.
PAGE 650
ATmega164A/PA/324A/PA/644A/PA/1284/P 34.8 ATmega1284P Speed [MHz] (3) 20 20 Notes: Power supply Ordering code (2) Package (1) 1.8 - 5.5V ATmega1284P-AU ATmega1284P-AUR(4) ATmega1284P-PU ATmega1284P-MU ATmega1284P-MUR(4) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 85oC) 1.8 - 5.5V ATmega1284P-AN ATmega1284P-ANR(4) ATmega1284P-PN ATmega1284P-MN ATmega1284P-MNR(4) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 105oC) Operational range 1. This device can also be supplied in wafer form.
PAGE 651
ATmega164A/PA/324A/PA/644A/PA/1284/P 35. Packaging information 35.1 44A PIN 1 IDENTIFIER PIN 1 B e E1 E A1 A2 D1 D C 0°~7° A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum.
PAGE 652
ATmega164A/PA/324A/PA/644A/PA/1284/P 35.2 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2.
PAGE 653
ATmega164A/PA/324A/PA/644A/PA/1284/P 35.3 44M1 D D Marked Pin# 1 I D Marked Pin# 1 I D E E SE ATING PLAN E SE ATING A1PLAN E TOP VIE W A1 A3 TOP VIE W L L A K Pin #1 Co rner D2 D2 Pin #1 Co rner 1 1 2 2 3 3 E2 E2 Option A Option A Option B Option B K K A3 A K e b e b B OT TOM VIE W Option C Option C SIDE VIEW SIDE VIEW Pin #1 Triangle Pin #1 Triangle Pin #1 Cham fer Pin #1 (C 0.30) Cham fer (C 0.30) Pin #1 Pin Notch #1 (0.20 R) Notch (0.
PAGE 654
ATmega164A/PA/324A/PA/644A/PA/1284/P 35.4 44MC C Pin 1 ID D SIDE VIEW y A1 E A TOP VIEW eT/2 A19 eR A24 B20 B16 A1 A18 COMMON DIMENSIONS (Unit of Measure = mm) B1 B15 b R0.20 0.40 SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.23 0.30 D2 eT C B5 B11 A6 A13 B10 B6 A12 0.20 REF D 4.90 5.00 5.10 D2 2.55 2.60 2.65 E 4.90 5.00 5.10 E2 2.55 2.60 2.65 eT – 0.70 – eR – 0.40 – A7 L L E2 L BOTTOM VIEW Note: NOTE 1.
PAGE 655
ATmega164A/PA/324A/PA/644A/PA/1284/P 35.5 49C2 E A1 BALL ID 0.10 D A1 TOP VIEW A A2 SIDE VIEW E1 G e F E D D1 COMMON DIMENSIONS (Unit of Measure = mm) C B SYMBOL A 1 A1 BALL CORNER 2 3 4 5 b 6 7 e 49 - Ø0.35 ±0.05 BOTTOM VIEW MIN NOM MAX A – – 1.00 A1 0.20 – – A2 0.65 – – D 4.90 5.00 5.10 D1 E 4.90 3.90 BSC 5.00 5.10 E1 b NOTE 3.90 BSC 0.30 0.35 e 0.40 0.65 BSC 3/14/08 TITLE 49C2, 49-ball (7 x 7 array), 0.65mm pitch, 5.0 x 5.0 x 1.
PAGE 656
ATmega164A/PA/324A/PA/644A/PA/1284/P 36. Errata 36.1 Errata for ATmega164A 36.1.1 Rev. E No known Errata. 36.2 Errata for ATmega164PA 36.2.1 Rev. E No known Errata. 36.3 Errata for ATmega324A 36.3.1 Rev. F No known Errata. 36.4 Errata for ATmega324PA 36.4.1 Rev. F No known Errata. 36.5 Errata for ATmega644A 36.5.1 Rev. F No known Errata. 36.6 Errata for ATmega644PA 36.6.1 Rev. F No known Errata. 36.7 Errata for ATmega1284 36.7.1 Rev. B No known Errata. 36.
PAGE 657
ATmega164A/PA/324A/PA/644A/PA/1284/P 37. Data sheet revision history Note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 37.1 Rev. A - 10/2018 1. 37.2  Updated the data sheet to Microchip style.  New Microchip document number. Previous version was Atmel data sheet rev. 8272G. Rev. 8272G - 01/2015 1.
PAGE 658
ATmega164A/PA/324A/PA/644A/PA/1284/P 37.4 Rev. 8272E - 04/2013 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 37.5 3. 4. 5. 6. Updated the Assembly code example for WDT_off (p.56) following the ej# 705736. Added note in ”16-bit Timer/Counter1 and Timer/Counter3(1) with PWM” on page 115. Added ”Prescaler Reset” on page 120. Corrected three typo for Waveform generation mode (WGM) instead of MGM. Updated Table 23-6 on page 261.
PAGE 659
ATmega164A/PA/324A/PA/644A/PA/1284/P 37.8 10. Updated ”Alternate Functions of Port D” on page 94 to include Timer/Counter3 11. Added ”TCNT3H and TCNT3L –Timer/Counter3” on page 140 12. Added ”OCR3AH and OCR3AL – Output Compare Register3 A” on page 141 13. Added ”OCR3BH and OCR3BL – Output Compare Register3 B” on page 141 14. Added ”TIMSK3 – Timer/Counter3 Interrupt Mask Register” on page 142 15.
PAGE 660
ATmega164A/PA/324A/PA/644A/PA/1284/P The Microchip Web Site Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 661
ATmega164A/PA/324A/PA/644A/PA/1284/P Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 662
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.