Datasheet

14.1.2.9. Pin Change Mask Register 3

Name: PCMSK3

Offset: 0x73

Reset: 0x00

Property:

Bit 7 6 5 4 3 2 1 0

PCINT31 PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT24, PCINT25, PCINT26, PCINT27, PCINT28, PCINT29, PCINT30,

PCINT31: Pin Change Enable Mask

Each PCINT[31:24]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If

PCINT[31:24] is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on the

corresponding I/O pin. If PCINT[31:24] is cleared, pin change interrupt on the corresponding I/O pin is

disabled.

Atmel ATmega644A [DATASHEET]

Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016