Datasheet

14.1.2.3. External Interrupt Flag Register

When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

The device is a complex microcontroller with more peripheral units than can be supported within the 64

locations reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 in

SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Name: EIFR

Offset: 0x3C

Reset: 0x00

Property:

When addressing as I/O Register: address offset is 0x1C

Bit 7 6 5 4 3 2 1 0

INTF2 INTF1 INTF0

Access

R/W R/W R/W

Reset 0 0 0

Bit 2 – INTF2: External Interrupt Flag 2

When an edge or logic change on the INT2 pin triggers an interrupt request, INTF2 will be set. If the I-bit

in SREG and the INT2 bit in EIMSK are set, the MCU will jump to the corresponding Interrupt Vector. The

flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to

it. This flag is always cleared when INT2 is configured as a level interrupt.

Bit 1 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 will be set. If the I-bit

in SREG and the INT1 bit in EIMSK are set, the MCU will jump to the corresponding Interrupt Vector. The

flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to

it. This flag is always cleared when INT1 is configured as a level interrupt.

Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 will be set. If the I-bit

in SREG and the INT0 bit in EIMSK are set, the MCU will jump to the corresponding Interrupt Vector. The

flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to

it. This flag is always cleared when INT0 is configured as a level interrupt.

Atmel ATmega644A [DATASHEET]

Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016