Datasheet

Figure 12-1. Reset Logic
MCU S ta tus
Register (MCUSR)
Brown-out
Rese t Circuit
BODLEVEL [2..0]
Delay Counte rs
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
Genera tor
SPIKE
FILTER
Pull-up Re sistor
JTRF
JTAG Rese t
Register
Watchdog
Oscillator
SUT[1:0]
Power-on Rese t
Circuit
Related Links
IEEE 1149.1 (JTAG) Boundary-scan on page 331
12.3. Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The POR is activated
whenever V
CC
is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on
Reset threshold voltage invokes the delay counter, which determines how long the device is kept in Reset
after V
CC
rise. The Reset signal is activated again, without any delay, when V
CC
decreases below the
detection level.
Figure 12-2. MCU Start-up, RESET Tied to V
CC
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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