Datasheet

11.12.1. Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: SMCR
Offset: 0x53
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x33
Bit 7 6 5 4 3 2 1 0
SM2 SM1 SM0 SE
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 3 – SM2: Sleep Mode Select 2
The SM[2:0] bits select between the five available sleep modes.
Table 11-2. Sleep Mode Select
SM2,SM1,SM0 Sleep Mode
000 Idle
001 ADC Noise Reduction
010 Power-down
011 Power-save
100 Reserved
101 Reserved
110 Standby
(1)
111 Extended Standby
(1)
Note:
1. Standby mode is only recommended for use with external crystals or resonators.
Bit 2 – SM1: Sleep Mode Select 1
Refer to SM2.
Bit 1 – SM0: Sleep Mode Select 0
Refer to SM2.
Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose,
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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