Datasheet

disable the BOD by software for some of the sleep modes. The sleep mode power consumption will then
be at the same level as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD
function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is
automatically enabled again. This ensures safe operation in case the V
CC
level has dropped during the
sleep period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60μs to
ensure that the BOD is working correctly before the MCU continues executing code.
BOD disable is controlled by the BOD Sleep bit in the MCU Control Register (MCUCR.BODS). Writing
this bit to '1' turns off the BOD in relevant sleep modes, while a zero in this bit keeps BOD active. The
default setting, BODS=0, keeps BOD active.
Note: Writing to the BODS bit is controlled by a timed sequence and an enable bit.
Related Links
MCUCR on page 64
Fuse Bits on page 363
11.4. Idle Mode
When the SM[2:0] bits are written to '000', the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the SPI, USART, Analog Comparator, 2-wire Serial Interface, Timer/
Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts
clk
CPU
and clk
FLASH
, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the
Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator
interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the
Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle
mode.
Related Links
ACSR on page 299
11.5. ADC Noise Reduction Mode
When the SM[2:0] bits are written to '001', the SLEEP instruction makes the MCU enter ADC Noise
Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-wire Serial
Interface address watch, Timer/Counter
(1)
, and the Watchdog to continue operating (if enabled). This
sleep mode basically halts clk
I/O
, clk
CPU
, and clk
FLASH
, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC
is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC Conversion
Complete interrupt, only these events can wake up the MCU from ADC Noise Reduction mode:
• External Reset
• Watchdog System Reset
• Watchdog Interrupt
• Brown-out Reset
• 2-wire Serial Interface address match
• Timer/Counter interrupt
• SPM/EEPROM ready interrupt
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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