Datasheet

source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk

I/O

clk

ADC

, clk

CPU

, and clk

FLASH

are divided by a factor as shown in the CLKPR description.

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs

in the clock system. It also ensures that no intermediate frequency is higher than neither the clock

frequency corresponding to the previous setting, nor the clock frequency corresponding to the new

setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of

the prescaler - even if it were readable, the exact time it takes to switch from one clock division to the

other cannot be exactly predicted. From the time the Clock Prescaler Selection bits (CLKPS[3:0]) values

are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this

interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period

corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change

the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to '1' and all other bits in CLKPR to zero:

CLKPR=0x80.

2. Within four cycles, write the desired value to CLKPS[3:0] while writing a zero to CLKPCE:

CLKPR=0x0N

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not

interrupted.