Datasheet

Mnemonic Operands Description Op Flags #Clocks
CLN Clear Negative Flag N ← 0 N 1
SEZ Set Zero Flag Z ← 1 Z 1
CLZ Clear Zero Flag Z ← 0 Z 1
SEI Global Interrupt Enable I ← 1 I 1
CLI Global Interrupt Disable I ← 0 I 1
SES Set Signed Test Flag S ← 1 S 1
CLS Clear Signed Test Flag S ← 0 S 1
SEV Set Two’s Complement Overflow V ← 1 V 1
CLV Clear Two’s Complement Overflow V ← 0 V 1
SET Set T in SREG T ← 1 T 1
CLT Clear T in SREG T ← 0 T 1
SEH Set Half Carry Flag in SREG H ← 1 H 1
CLH Clear Half Carry Flag in SREG H ← 0 H 1
Table 31-5. MCU Control Instructions
Mnemonic Operands Description Operation Flags #Clocks
BREAK Break (See also in Debug interface description) None 1
NOP No Operation None 1
SLEEP Sleep (see also power management and sleep description) None 1
WDR Watchdog Reset (see also Watchdog Controller description) None 1
Note:
1. Cycle time for data memory accesses assume internal RAM access, and are not valid for accesses
through the NVM controller. A minimum of one extra cycle must be added when accessing memory
through the NVM controller (such as Flash and EEPROM), but depending on simultaneous
accesses by other masters or the NVM controller state, there may be more than one extra cycle.
2. One extra cycle must be added when accessing lower (64 bytes of) I/O space.
3. The instruction is not available on all devices.
4. Device dependent. Please see the device specific datasheet.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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