Datasheet

Mnemonic Operands Description Op Flags #Clocks
ELPM Rd, Z+ Extended Load Program Memory and
Post-Increment
Rd
(RAMPZ:Z)
←
←
(RAMPZ:Z)
(RAMPZ:Z) + 1
None 3
SPM Store Program Memory (RAMPZ:Z) ← R1:R0 None
(4)
SPM Z+ Store Program Memory and Post-
Increment by 2
(RAMPZ:Z)
Z
←
←
R1:R0
Z + 2
None
(4)
IN Rd, A In From I/O Location Rd ← I/O(A) None 1
OUT A, Rr Out To I/O Location I/O(A) ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2
XCH Z, Rd Exchange (Z)
Rd
←
←
Rd
(Z)
None N/A
LAS Z, Rd Load and Set (Z)
Rd
←
←
Rd v (Z)
(Z)
None N/A
LAC Z, Rd Load and Clear (Z)
Rd
←
←
($FF – Rd) • (Z)
(Z)
None N/A
LAT Z, Rd Load and Toggle (Z)
Rd
←
←
Rd ⊕ (Z)
(Z)
None N/A
Table 31-4. Bit and Bit-test Instructions
Mnemonic
Operands Description Op Flags #Clocks
LSL Rd Logical Shift Left Rd(n+1)
Rd(0)
C
←
←
←
Rd(n)
0
Rd(7)
Z,C,N,V,H 1
LSR Rd Logical Shift Right Rd(n)
Rd(7)
C
←
←
←
Rd(n+1)
0
Rd(0)
Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)
Rd(n+1)
C
←
←
←
C
Rd(n)
Rd(7)
Z,C,N,V,H 1
ROR Rd Rotate Right Through Carry Rd(7)
Rd(n)
C
←
←
←
C
Rd(n+1)
Rd(0)
Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0) ↔ Rd(7..4) None 1
SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 2
CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None 2
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← T None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
SEC Set Carry C ← 1 C 1
CLC Clear Carry C ← 0 C 1
SEN Set Negative Flag N ← 1 N 1
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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