Datasheet

Figure 29-6. Parallel programming timing, including some general timing requirements.
Data & Contol
(DATA, XA0/1, BS 1, BS 2)
XTAL1
t
XHXL
t
WLWH
t
DVXH
t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
PAGEL
t
PHP L
t
PLBX
t
BVP H
t
XLWL
t
WLBX
t
BVWL
WLRL
Figure 29-7. Parallel programming timing, loading sequence with timing requirements
.
XTAL1
PAGEL
t
PLXH
XLXH
t
t
XLPH
ADDR0 (Low Byte ) DATA (Low Byte ) DATA (High Byte ) ADDR1 (Low Byte )
DATA
BS1
XA0
XA1
LOAD ADDRES S
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRES S
(LOW BYTE)
Note: The timing requirements shown in Figure 29-6 (that is, t
DVXH
, t
XHXL
, and t
XLDX
) also apply to
loading operation.
Figure 29-8. Parallel programming timing, reading sequence (within the same page) with timing requirements
XTAL1
OE
ADDR0 (Low Byte ) DATA (Low Byte )
DATA (High Byte )
ADDR1 (Low Byte )
DATA
BS1
XA0
XA1
LOAD ADDRES S
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRES S
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ
Note: The timing requirements shown in Figure 29-6 (that is, t
DVXH
, t
XHXL
, and t
XLDX
) also apply to
loading operation.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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