Datasheet

Figure 28-9. State Machine Sequence for Changing the Instruction Word
Te st-Logic-Re s e t
Run-Te s t/Idle
Shift-DR
Exit1-DR
Paus e-DR
Exit2-DR
Update -DR
Se lect-IR S can
Ca pture-IR
Shift-IR
Exit1-IR
Paus e-IR
Exit2-IR
Update -IR
Se lect-DR Scan
Ca pture-DR
0
1
0
1 1 1
0 0
0 0
1 1
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
00
11
28.10.2. AVR_RESET (0xC)
The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the
device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset
Register is selected as Data Register. Note that the reset will be active as long as there is a logic 'one' in
the Reset Chain. The output from this chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
Atmel ATmega644A [DATASHEET]
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