Datasheet

Figure 28-6. Serial Programming and Verify
VCC
GND
EXTCLK
SCK
MISO
MOSI
RESET
+1.8 - 5.5V
AVCC
+1.8 - 5.5V
(2)
Note:
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. V
CC
- 0.3V < AVCC < V
CC
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation
(in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip
Erase operation turns the content of every memory location in both the Program and EEPROM arrays
into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the
serial clock (SCK) input are defined as follows:
• Low: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
≥ 12MHz
• High: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
≥ 12MHz
28.9.1. Serial Programming Pin Mapping
Table 28-17. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI PB5 I Serial Data in
MISO PB6 O Serial Data out
SCK PB7 I Serial Clock
Note: The pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the
internal SPI interface.
28.9.2. Serial Programming Algorithm
When writing serial data to the device, data is clocked on the rising edge of SCK.
When reading data from the device, data is clocked on the falling edge of SCK. Please refer to the figure,
Serial Programming Waveforms in SPI Serial Programming Characteristics section for timing details.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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