Datasheet

Figure 26-6. General Port Pin Schematic diagram
CLK
RPx
RRx
WPx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WPx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ P ORTx P IN
PUD: P ULLUP DISABLE
CLK : I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RES ET
RES ET
Q
Q
D
Q
Q
D
CLR
PORTxn
Q
Q
D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP : SLEEP CONTROL
Pxn
I/O
I/O
Se e Boundary-Sca n de s cription
for de ta ils!
PUExn
OCxn
ODxn
IDxn
PUExn: PULLUP ENABLE for pin Pxn
OCxn: OUTP UT CONTROL for pin P xn
ODxn: OUTPUT DATA to pin Pxn
IDxn: INP UT DATA from pin Pxn
Related Links
I/O-Ports on page 95
26.13.2. Scanning the RESET Pin
The RESET pin accepts 5V active low logic for standard Reset operation, and 12V active high logic for
High Voltage Parallel programming. An observe-only cell as shown in the figure below is inserted both for
the 5V Reset signal; RSTT, and the 12V Reset signal; RSTHV.
Figure 26-7. Observe-only Cell
0
1
D Q
From
pre vious
ce ll
ClockDR
ShiftDR
To
ne xt
ce ll
From s ys te m pin
To s ys te m logic
FF1
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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