Datasheet

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must
be taken when updating the ADMUX Register, in order to control which conversion will be affected by the
new settings.
If both the ADC Auto Trigger Enable and ADC Enable bits (ADCRSA.ADATE, ADCRSA.ADEN) are
written to '1', an interrupt event can occur at any time. If the ADMUX Register is changed in this period,
the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely
updated in the following ways:
1. When ADATE or ADEN is cleared.
1.1. During conversion, minimum one ADC clock cycle after the trigger event.
1.2. After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
Special care should be taken when changing differential channels. Once a differential channel has been
selected, the gain stage may take as much as 125 μs to stabilize to the new value. Thus conversions
should not be started within the first 125 μs after selecting a new differential channel. Alternatively,
conversion results obtained within this period should be discarded. The same settling time should be
observed for the first differential conversion after changing ADC reference (by changing the REFS[1:0]
bits in ADMUX).
25.5.1. ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure that the
correct channel is selected:
• In Single Conversion mode, always select the channel before starting the conversion. The channel
selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest
method is to wait for the conversion to complete before changing the channel selection.
• In Free Running mode, always select the channel before starting the first conversion. The channel
selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest
method is to wait for the first conversion to complete, and then change the channel selection. Since
the next conversion has already started automatically, the next result will reflect the previous
channel selection. Subsequent conversions will reflect the new channel selection.
The user is advised not to write new channel or reference selection values during Free Running mode.
When switching to a differential gain channel, the first conversion result may have a poor accuracy due to
the required settling time for the automatic offset cancellation circuitry. The user should preferably
disregard the first conversion result.
25.5.2. ADC Voltage Reference
The reference voltage for the ADC (V
REF
) indicates the conversion range for the ADC. Single ended
channels that exceed V
REF
will result in codes close to 0x3FF. V
REF
can be selected as either AV
CC
,
internal 2.56V reference, or external AREF pin.
AV
CC
is connected to the ADC through a passive switch. The internal 2.56V reference is generated from
the internal bandgap reference (V
BG
) through an internal amplifier. In either case, the external AREF pin
is directly connected to the ADC, and the reference voltage can be made more immune to noise by
connecting a capacitor between the AREF pin and ground. V
REF
can also be measured at the AREF pin
with a high impedance voltmeter. Note that V
REF
is a high impedance source, and only a capacitive load
should be connected in a system.
If the user has a fixed voltage source connected to the AREF pin, the user may not use the other
reference voltage options in the application, as they will be shorted to the external voltage. If no external
voltage is applied to the AREF pin, the user may switch between AV
CC
and 2.56V as reference selection.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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