Datasheet

writing to the REFSn bits in the ADMUX Register. The internal voltage reference must be decoupled by
an external capacitor at the AREF pin to improve noise immunity.
Figure 25-1. Analog to Digital Converter Block Schematic Operation
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
15 0
ADC MULTIPLEXER
SELECT (ADMUX)
ADC CTRL. & ST ATUS
REGISTER (ADCSRA)
ADC DATA REGISTER
(ADCH/ADCL)
MUX2
ADIE
ADATE
ADSC
ADEN
ADIF
ADIF
MUX1
MUX0
ADPS0
ADPS1
ADPS2
MUX3
CONVERSION LOGIC
10-BIT DAC
+
-
SAMPLE & HOLD
COMPARATOR
INTERNAL
REFERENCE
MUX DECODER
AVCC
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
REFS0
REFS1
ADLAR
CHANNEL SELECTION
ADC[9:0]
ADC MULTIPLEXER
OUTPUT
AREF
BANDGAP
REFERENCE
PRESCALER
AGND
MUX4
+
-
SINGLE ENDED / DIFFERENTIAL SELECTION
POS.
INPUT
MUX
NEG.
INPUT
MUX
TRIGGER
SELECT
ADTS[2:0]
INTERRUPT
FLAGS
START
The analog input channel is selected by writing to the MUX bits in the ADC Multiplexer Selection register
ADMUX.MUX[4:0]. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference,
can be selected as single ended inputs to the ADC. The ADC is enabled by writing a '1' to the ADC
Enable bit in the ADC Control and Status Register A (ADCSRA.ADEN). Voltage reference and input
channel selections will not take effect until ADEN is set. The ADC does not consume power when ADEN
is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes.
If differential channels are selected, the differential gain stage amplifies the voltage difference between
the selected input channel pair by the selected gain factor. This amplified value then becomes the analog
input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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