Datasheet

25. ADC - Analog to Digital Converter
25.1. Features
• 10-bit Resolution
• 0.5 LSB Integral Non-Linearity
• ±2 LSB Absolute Accuracy
• 13 - 260μs Conversion Time
• Up to 15kSPS at Maximum Resolution
• 8 Multiplexed Single Ended Input Channels
• Differential mode with selectable gain at 1x, 10x or 200x
(1)
• Optional Left Adjustment for ADC Result Readout
• 0 - V
CC
ADC Input Voltage Range
• 2.7V - V
CC
Differential ADC Voltage Range
• Selectable 2.56V or 1.1V ADC Reference Voltage
• Free Running or Single Conversion Mode
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler
Note:
1. The differential input channels are not tested for devices in PDIP Package. This feature is only
guaranteed to work for devices in TQFP and VQFN/QFN/MLF Packages.
25.2. Overview
The device features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel
Analog Multiplexer which allows 8 single-ended voltage inputs constructed from the pins of Port A. The
single-ended voltage inputs refer to 0V (GND).
The device also supports 16 differential voltage input combinations. Two of the differential inputs (ADC1,
ADC0 and ADC3, ADC2) are equipped with a programmable gain stage. This provides amplification steps
of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage before the A/D conversion.
Seven differential analog input channels share a common negative terminal (ADC1), while any other ADC
input can be selected as the positive input terminal. If 1x or 10x gain is used, 8-bit resolution can be
expected. If 200x gain is used, 6- bit resolution can be expected. Note that internal references of 1.1V
should not be used on 10x and 200x gain.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a
constant level during conversion. A block diagram of the ADC is shown below.
The ADC has a separate analog supply voltage pin, AV
CC
. AV
CC
must not differ more than ±0.3V from
V
CC
. See section ADC Noise Canceler on how to connect this pin.
The Power Reduction ADC bit in the Power Reduction Register (PRR.PRADC) must be written to '0' in
order to be enable the ADC.
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The
minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1
LSB. Optionally, AV
CC
or an internal 2.56V reference voltage may be connected to the AREF pin by
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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