Datasheet

24.3.2. Digital Input Disable Register 1
Name: DIDR1
Offset: 0x7F
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
Reserved5 Reserved4 Reserved3 Reserved2 Reserved1 Reserved0 AIN1D AIN0D
Access
R R R R R R R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 2, 3, 4, 5, 6, 7 – Reservedn
Bits 0, 1 – AIN0D, AIN1D: AIN Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding
PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the
AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce
power consumption in the digital input buffer.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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