Datasheet

Table 23-7. Miscellaneous States
Status Code
(TWSR)
Prescaler Bits are
0
Status of the 2-wire Serial
Bus and 2-wire Serial
Interface Hardware
Application Software Response Next Action Taken by
TWI Hardware
To/from
TWDRn
To TWCRn
STA STO TWINT TWEA
0xF8 No relevant state information
available; TWINT = “0”
No TWDRn
action
No TWCRn action Wait or proceed current
transfer
0x00 Bus error due to an illegal
START or STOP condition
No TWDRn
action
0 1 1 X Only the internal hardware
is affected, no STOP
condition is sent on the
bus. In all cases, the bus is
released and TWSTO is
cleared.
23.7.6. Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action. Consider
for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the
Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read
from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The
Master must keep control of the bus during all these steps, and the steps should be carried out as an
atomical operation. If this principle is violated in a multi master system, another Master can alter the data
pointer in the EEPROM between steps 2 and 3, and the Master will read the wrong data location. Such a
change in transfer direction is accomplished by transmitting a REPEATED START between the
transmission of the address byte and reception of the data. After a REPEATED START, the Master keeps
ownership of the bus. The flow in this transfer is depicted in the following figure:
Figure 23-19. Combining Several TWI Modes to Access a Serial EEPROM
Master Transmitter Master Receiv er
S = ST AR T Rs = REPEA TED ST AR T P = ST OP
Transmitted from master to sla v e Transmitted from sla v e to master
S SLA+W A ADDRESS A Rs SLA+R A DATA A P
23.8. Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one
or more of them. The TWI standard ensures that such situations are handled in such a way that one of
the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An
example of an arbitration situation is depicted below, where two masters are trying to transmit data to a
Slave Receiver.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
287