Datasheet

Figure 23-12. Formats and States in the Master Transmitter Mode
S SLA W A DAT A A P
0x08 0x18 0x28
R SLA W
0x10
A P
0x20
P
0x30
A or A
0x38
A
Other master
contin ues
A or A
0x38
Other master
contin ues
R
A
0x68
Other master
contin ues
0x78 0xB0
To corresponding
states in sla v e mode
MT
MR
Successfull
transmission
to a sla v e
receiv er
Next transfer
star ted with a
repeated star t
condition
Not acknowledge
received after the
slave address
Not acknowledge
receiv ed after a data
byte
Arbitration lost in sla v e
address or data b yte
Arbitration lost and
addressed as sla v e
DAT A A
n
From master to sla v e
From sla v e to master
Any number of data b ytes
and their associated ac kno wledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Ser ial Bus. The
prescaler bits are z ero or mask ed to z ero
S
23.7.2. Master Receiver Mode
In the Master Receiver (MR) mode, a number of data bytes are received from a Slave Transmitter (see
next figure). In order to enter a Master mode, a START condition must be transmitted. The format of the
following address packet determines whether Master Transmitter (MT) or MR mode is to be entered. If
SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status
codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
Atmel ATmega644A [DATASHEET]
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