Datasheet

data packets. In other words; All transmissions must contain the same number of data packets, otherwise
the result of the arbitration is undefined.
23.5. Overview of the TWI Module
The TWI module is comprised of several submodules, as shown in the following figure. The registers
drawn in a thick line are accessible through the AVR data bus.
Figure 23-9. Overview of the TWI Module
TWI Unit
Address Register
(TW AR)
Address Match Unit
Address Comparator
Control Unit
Control Register
(TWCR)
Status Register
(TWSR)
State Machine and
Status control
SCL
Sle w-r ate
Control
Spik e
Filter
SD A
Sle w-r ate
Control
Spik e
Filter
Bit Rate Gener ator
Bit Rate Register
(TWBR)
Prescaler
Bus Interf ace Unit
ST AR T / ST OP
Control
Arbitration detection Ack
Spik e Suppression
Address/Data Shift
Register (TWDR)
23.5.1. SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-
rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit
removing spikes shorter than 50ns. Note that the internal pull-ups in the AVR pads can be enabled by
setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section. The
internal pull-ups can in some systems eliminate the need for external ones.
23.5.2. Bit Rate Generator Unit
This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by
settings in the TWI Bit Rate Register (TWBRn) and the Prescaler bits in the TWI Status Register
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
264