Datasheet

BAUD Baud rate (in bits per second, bps)
f
OSC
System Oscillator clock frequency
UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095)
22.4. SPI Data Modes and Timing
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are
determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in the
following figure. Data bits are shifted out and latched in on opposite edges of the XCKn signal, ensuring
sufficient time for data signals to stabilize. The UCPOLn and UCPHAn functionality is summarized in the
following table. Note that changing the setting of any of these bits will corrupt all ongoing communication
for both the Receiver and Transmitter.
Table 22-2. UCPOLn and UCPHAn Functionality
UCPOLn UCPHAn SPI Mode Leading Edge Trailing Edge
0 0 0 Sample (Rising) Setup (Falling)
0 1 1 Setup (Rising) Sample (Falling)
1 0 2 Sample (Falling) Setup (Rising)
1 1 3 Setup (Falling) Sample (Rising)
Figure 22-1. UCPHAn and UCPOLn data transfer timing diagrams.
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
UCPOL=0 UCPOL=1
UCPHA=0
UCPHA=1
22.5. Frame Formats
A serial frame for the MSPIM is defined to be one character of eight data bits. The USART in MSPIM
mode has two valid frame formats:
• 8-bit data with MSB first
• 8-bit data with LSB first
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are
succeeding, ending with the most or least significant bit accordingly. When a complete frame is
transmitted, a new frame can directly follow it, or the communication line can be set to an idle (high) state.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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