Datasheet

filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous
reception operational range depends on the accuracy of the internal baud rate clock, the rate of the
incoming frames, and the frame size in number of bits.
21.9.1. Asynchronous Clock Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames. The figure below
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16-times the
baud rate for Normal mode, and 8 times the baud rate for Double Speed mode. The horizontal arrows
illustrate the synchronization variation due to the sampling process. Note the larger time variation when
using the Double Speed mode (UCSRnA.U2X=1) of operation. Samples denoted '0' are samples taken
while the RxDn line is idle (i.e., no communication activity).
Figure 21-5. Start Bit Sampling
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2
STARTIDLE
00
BIT 0
3
1 2 3 4 5 6 7 8 1 20
RxDn
Sample
(U2X = 0)
Sample
(U2X = 1)
When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit
detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The
clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and samples 4, 5, and 6 for Double
Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is
received. If two or more of these three samples have logical high levels (the majority wins), the start bit is
rejected as a noise spike and the Receiver starts looking for the next high to low-transition on RxDn. If
however, a valid start bit is detected, the clock recovery logic is synchronized and the data recovery can
begin. The synchronization process is repeated for each start bit.
21.9.2. Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery
unit uses a state machine that has 16 states for each bit in Normal mode and eight states for each bit in
Double Speed mode. The figure below shows the sampling of the data bits and the parity bit. Each of the
samples is given a number that is equal to the state of the recovery unit.
Figure 21-6. Sampling of Data and Parity Bit
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
BIT n
1 2 3 4 5 6 7 8 1
RxDn
Sample
(U2X = 0)
Sample
(U2X = 1)
The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to
the three samples in the center of the received bit: If two or all three center samples (those marked by
their sample number inside boxes) have high levels, the received bit is registered to be a logic '1'. If two
or all three samples have low levels, the received bit is registered to be a logic '0'. This majority voting
process acts as a low pass filter for the incoming signal on the RxDn pin. The recovery process is then
repeated until a complete frame is received, including the first stop bit. The Receiver only uses the first
stop bit of a frame.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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