Datasheet

BAUD Baud rate (in bits per second, bps)
f
OSC
System oscillator clock frequency
UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095).
Some examples of UBRRn values for some system clock frequencies are found in Examples
of Baud Rate Settings.
21.4.2. Double Speed Operation (U2X)
The transfer rate can be doubled by setting the U2X bit in UCSRnA. Setting this bit only has effect for the
asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer
rate for asynchronous communication. However, in this case, the Receiver will only use half the number
of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate
baud rate setting and system clock are required when this mode is used.
For the Transmitter, there are no downsides.
21.4.3. External Clock
External clocking is used by the synchronous slave modes of operation. The description in this section
refers to the Clock Generation Logic block diagram in the previous section.
External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance
of meta-stability. The output from the synchronization register must then pass through an edge detector
before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period
delay and therefore the maximum external XCKn clock frequency is limited by the following equation:

XCKn
<

OSC
4
The value of f
osc
depends on the stability of the system clock source. It is therefore recommended to add
some margin to avoid possible loss of data due to frequency variations.
21.4.4. Synchronous Clock Operation
When synchronous mode is used (UMSEL = 1), the XCKn pin will be used as either clock input (Slave) or
clock output (Master). The dependency between the clock edges and data sampling or data change is the
same. The basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the
edge the data output (TxDn) is changed.
Figure 21-3. Synchronous Mode XCKn Timing
RxDn / TxDn
XCKn
RxDn / TxDn
XCKn UCPOL = 0
UCPOL = 1
Sample
Sample
The UCPOL bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for
data change. As the above timing diagram shows, when UCPOL is zero, the data will be changed at
Atmel ATmega644A [DATASHEET]
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