Datasheet

Table 20-4. CPHA0 Functionality
CPHA0 Leading Edge Trailing Edge
0 Sample Setup
1 Setup Sample
Bits 1:0 – SPR0n: SPI0 Clock Rate Select n [n = 1:0]
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect
on the Slave. The relationship between SCK and the Oscillator Clock frequency f
osc
is shown in the table
below.
Table 20-5. Relationship between SCK and Oscillator Frequency
SPI2X SPR01 SPR00 SCK Frequency
0 0 0 f
osc
/4
0 0 1 f
osc
/16
0 1 0 f
osc
/64
0 1 1 f
osc
/128
1 0 0 f
osc
/2
1 0 1 f
osc
/8
1 1 0 f
osc
/32
1 1 1 f
osc
/64
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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