Datasheet

19.11.7. TC2 Interrupt Flag Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: TIFR2
Offset: 0x37
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x17
Bit 7 6 5 4 3 2 1 0
OCFB OCFA TOV
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – OCFB: Timer/Counter2, Output Compare B Match Flag
The OCFB bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in
OCRB – Output Compare Register2. OCFB is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, OCFB is cleared by writing a logic one to the flag. When the I-bit in
SREG, OCIEB (Timer/Counter2 Compare match Interrupt Enable), and OCFB are set (one), the Timer/
Counter2 Compare match Interrupt is executed.
Bit 1 – OCFA: Timer/Counter2, Output Compare A Match Flag
The OCFA bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in
OCRA – Output Compare Register2. OCFA is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, OCFA is cleared by writing a logic one to the flag. When the I-bit in
SREG, OCIEA (Timer/Counter2 Compare match Interrupt Enable), and OCFA are set (one), the Timer/
Counter2 Compare match Interrupt is executed.
Bit 0 – TOV: Timer/Counter2, Overflow Flag
The TOV bit is set (one) when an overflow occurs in Timer/Counter2. TOV is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, TOV is cleared by writing a logic one
to the flag. When the SREG I-bit, TOIEA (Timer/Counter2 Overflow Interrupt Enable), and TOV are set
(one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/
Counter2 changes counting direction at 0x00.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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