Datasheet

19.11.6. TC2 Interrupt Mask Register
Name: TIMSK2
Offset: 0x70
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
OCIEB OCIEA TOIE
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – OCIEB: Timer/Counter2, Output Compare B Match Interrupt Enable
When the OCIEB bit is written to '1' and the I-bit in the Status Register is set (one), the Timer/Counter2
Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in
Timer/Counter2 occurs, i.e., when the OCFB bit is set in TIFR2.
Bit 1 – OCIEA: Timer/Counter2, Output Compare A Match Interrupt Enable
When the OCIEA bit is written to '1' and the I-bit in the Status Register is set (one), the Timer/Counter2
Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in
Timer/Counter2 occurs, i.e., when the OCFA bit is set in TIFR2.
Bit 0 – TOIE: Timer/Counter2, Overflow Interrupt Enable
When the TOIE bit is written to '1' and the I-bit in the Status Register is set (one), the Timer/Counter2
Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2
occurs, i.e., when the TOV bit is set in TIFR2.
Atmel ATmega644A [DATASHEET]
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