Datasheet

19.11.1. TC2 Control Register A
Name: TCCR2A
Offset: 0xB0
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
COM2A1 COM2A0 COM2B1 COM2B0 WGM21 WGM20
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 7:6 – COM2An: Compare Output Mode for Channel A [n = 1:0]
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A[1:0] bits are
set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However,
note that the Data Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to
enable the output driver.
When OC2A is connected to the pin, the function of the COM2A[1:0] bits depends on the WGM2[2:0] bit
setting. The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to a
normal or CTC mode (non- PWM).
Table 19-3. Compare Output Mode, non-PWM
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
0 1 Toggle OC2A on Compare Match.
1 0 Clear OC2A on Compare Match.
1 1 Set OC2A on Compare Match .
The table below shows the COM2A[1:0] bit functionality when the WGM2[1:0] bits are set to fast PWM
mode.
Table 19-4. Compare Output Mode, Fast PWM
(1)
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected
WGM22 = 1: Toggle OC2A on Compare Match
1 0 Clear OC2A on Compare Match, set OC2A at BOTTOM (non-inverting mode)
1 1 Set OC2A on Compare Match, clear OC2A at BOTTOM (inverting mode)
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case the compare
match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details.
The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to phase
correct PWM mode.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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