Datasheet

unpredictable, as it depends on the wake-up time. The recommended procedure for reading
TCNT2 is thus as follows:
1. Wait for the corresponding Update Busy Flag to be cleared.
2. Read TCNT2.
• During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous
timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one
before the processor can read the timer value causing the setting of the Interrupt Flag. The Output
Compare pin is changed on the timer clock and is not synchronized to the processor clock.
19.10. Timer/Counter Prescaler
Figure 19-12. Prescaler for TC2
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
clk
I/O
clk
T2S
TOSC1
AS2
CS20
CS21
CS22
clk
T2S
/8
clk
T2S
/64
clk
T2S
/128
clk
T2S
/1024
clk
T2S
/256
clk
T2S
/32
0
PSRASY
Clear
clk
T2
The clock source for TC2 is named clk
T2S
. It is by default connected to the main system I/O clock clk
I/O
.
By writing a '1' to the Asynchronous TC2 bit in the Asynchronous Status Register (ASSR.AS2), TC2 is
asynchronously clocked from the TOSC1 pin. This enables use of TC2 as a Real Time Counter (RTC).
When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port B. A crystal can then be
connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for TC2. The
Oscillator is optimized for use with a 32.768kHz crystal.
For TC2, the possible prescaled selections are: clk
T2S
/8, clk
T2S
/32, clk
T2S
/64, clk
T2S
/128, clk
T2S
/256, and
clk
T2S
/1024. Additionally, clk
T2S
as well as 0 (stop) may be selected. The prescaler is reset by writing a '1'
to the Prescaler Reset TC2 bit in the General TC2 Control Register (GTCCR.PSRASY). This allows the
user to operate with a defined prescaler.
19.11. Register Description
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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