Datasheet

0xFF when WGM2[2:0] = 0x3, and OCR2A when MGM2[2:0] = 7. In non-inverting Compare Output mode,

the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x while

upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the

operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope

operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are

preferred for motor control applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the

counter reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer

clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 19-7. The TCNT2

value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram

includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes

represent compare matches between OCR2x and TCNT2.

Figure 19-7. Phase Correct PWM Mode, Timing Diagram

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

1 2 3

TCNTn

Period

OCnx

(COMnx[1:0] = 2)

(COMnx[1:0] = 3)

OCRnx Update

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt

Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin.

Setting the COM2x[1:0] bits to two will produce a non-inverted PWM. An inverted PWM output can be

generated by setting the COM2x[1:0] to three. TOP is defined as 0xFF when WGM2[2:0] = 0x3, and

OCR2A when WGM2[2:0] = 7. The actual OC2x value will only be visible on the port pin if the data

direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the

OC2x Register at the compare match between OCR2x and TCNT2 when the counter increments, and

setting (or clearing) the OC2x Register at compare match between OCR2x and TCNT2 when the counter

decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the

following equation:

Atmel ATmega644A [DATASHEET]

Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016

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