Datasheet

by the Data Direction Register (DDR) for the port pin. In the Data Direction Register, the bit for the OC1x
pin (DDR.OC0x) must be set as output before the OC0x value is visible on the pin. The port override
function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x register state before the
output is enabled. Some TCCR0A.COM0x[1:0] bit settings are reserved for certain modes of operation.
The TCCR0A.COM0x[1:0] bits have no effect on the Input Capture unit.
Related Links
Register Description on page 139
16.6.1. Compare Output Mode and Waveform Generation
The Waveform Generator uses the TCCR0A.COM0x[1:0] bits differently in Normal, CTC, and PWM
modes. For all modes, setting the TCCR0A.COM0x[1:0]=0x0 tells the Waveform Generator that no action
on the OC0x Register is to be performed on the next compare match. Refer also to the descriptions of the
output modes.
A change of the TCCR0A.COM0x[1:0] bits state will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using the
TCCR0C.FOC0x strobe bits.
16.7. Modes of Operation
The mode of operation determines the behavior of the Timer/Counter and the Output Compare pins. It is
defined by the combination of the Waveform Generation mode bits and Compare Output mode
(TCCR0A.WGM0[2:0]) bits in the Timer/Counter control Registers A and B (TCCR0A.COM0x[1:0]). The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode
bits do. The COM0x[1:0] bits control whether the PWM output generated should be inverted or not
(inverted or non-inverted PWM). For non-PWM modes the COM0x[1:0] bits control whether the output
should be set, cleared, or toggled at a compare match (See previous section Compare Match Output
Unit).
For detailed timing information refer to the following section Timer/Counter Timing Diagrams.
Related Links
Compare Match Output Unit on page 193
Timer/Counter Timing Diagrams on page 137
16.7.1. Normal Mode
The simplest mode of operation is the Normal mode (WGM0[2:0] = 0x0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply overruns
when it passes its maximum 8-bit value (TOP=0xFF) and then restarts from the bottom (0x00). In Normal
mode operation, the Timer/Counter Overflow Flag (TOV0) will be set in the same clock cycle in which the
TCNT0 becomes zero. In this case, the TOV0 Flag behaves like a ninth bit, except that it is only set, not
cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the
timer resolution can be increased by software. There are no special cases to consider in the Normal
mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of
the CPU time.
Atmel ATmega644A [DATASHEET]
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