Datasheet

15.4.13. Port D Input Pins Address
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: PIND
Offset: 0x29
Reset: N/A
Property: When addressing as I/O Register: address offset is 0x09
Bit 7 6 5 4 3 2 1 0
PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset x x x x x x x x
Bits 7:0 – PINDn: Port D Input Pins Address [n = 7:0]
Writing to the pin register provides toggle functionality for IO. Refer to Toggling the Pin.
Atmel ATmega644A [DATASHEET]
Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016
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