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8-bit AVR Microcontrollers

ATmega644A

DATASHEET COMPLETE

Introduction

The Atmel

ATmega644A is a low-power CMOS 8-bit microcontroller based

on the AVR

enhanced RISC architecture. By executing powerful

instructions in a single clock cycle, the ATmega644A achieves throughputs

close to 1MIPS per MHz. This empowers system designer to optimize the

device for power consumption versus processing speed.

Feature

High Performance, Low Power Atmel

AVR

8-Bit Microcontroller Family

• Advanced RISC Architecture

– 131 Powerful Instructions

– Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory Segments

– 64KBytes of In-System Self-Programmable Flash Program

Memory

– 2KBytes EEPROM

– 4KBytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data Retention: 20 Years at 85°C/100 Years at 25°C

(1)

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Programming Lock for Software Security

• Atmel QTouch

Library Support

– Capacitive Touch Buttons, Sliders and Wheels

– QTouch and QMatrix acquisition

– Up to 64 Sense Channels

Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016

Summary of content (446 pages)

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8-bit AVR Microcontrollers ATmega644A DATASHEET COMPLETE Introduction ® The Atmel ATmega644A is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega644A achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed.
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• • JTAG (IEEE std. 1149.
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Table of Contents Introduction......................................................................................................................1 Feature............................................................................................................................ 1 1. Description.................................................................................................................9 2. Configuration Summary...........................................................................
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10.4. Full Swing Crystal Oscillator.......................................................................................................46 10.5. Low Frequency Crystal Oscillator...............................................................................................47 10.6. Calibrated Internal RC Oscillator................................................................................................48 10.7. 128kHz Internal Oscillator.................................................................
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16. TC0 - 8-bit Timer/Counter0 with PWM...................................................................127 16.1. 16.2. 16.3. 16.4. 16.5. 16.6. 16.7. 16.8. 16.9. Features................................................................................................................................... 127 Overview...................................................................................................................................127 Timer/Counter Clock Sources.................................
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20.2. Overview...................................................................................................................................214 20.3. SS Pin Functionality................................................................................................................. 218 20.4. Data Modes.............................................................................................................................. 218 20.5. Register Description..............................................
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25.4. Prescaling and Conversion Timing...........................................................................................305 25.5. 25.6. 25.7. 25.8. Changing Channel or Reference Selection.............................................................................. 308 ADC Noise Canceler................................................................................................................ 310 ADC Conversion Result............................................................................
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29.2. DC Characteristics....................................................................................................................395 29.3. Speed Grades.......................................................................................................................... 397 29.4. Clock Characteristics................................................................................................................398 29.5. System and Reset Characteristics..........................................
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1. Description The Atmel® ATmega644A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega644A achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed. The Atmel AVR® core combines a rich instruction set with 32 general purpose working registers.
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2. Configuration Summary The table below compares the device series of feature and pin compatible devices, providing a seamless migration path. Table 2-1.
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3. Ordering Information Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range 20 1.8 - 5.5 ATmega644A-AU 44A Industrial (-40°C to 85°C) ATmega644A-AUR(4) 44A ATmega644A-PU 40P6 ATmega644A-MU 44M1 ATmega644A-MUR(4) 44M1 Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
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4. Block Diagram Figure 4-1. Block Diagram SRAM TCK TMS TDI TDO JTAG CPU OCD Clock generation TOSC1 32.
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5. Pin Configurations 5.1. Pinout 5.1.1.
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PB1 (T1/CLKO/PCINT9) PB0 (XCK0/T0/PCINT8) GND VCC PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) 41 40 39 38 37 36 35 34 Crystal/Osc PB2 (AIN0/INT2/PCINT10) Analog 42 Digital PB3 (AIN1/OC0A/PCINT11) Programming/debug 43 Ground PB4 (SS/OC0B/PCINT12) Power 44 TQFN and QFN GND XTAL2 7 27 AVCC XTAL1 8 26 PC7 (TOSC2/PCINT23) (PCINT24/RXD0) PD0 9 25 PC6 (TOSC1/PCINT22) (PCINT25/TXD0) PD1 10 24 PC5 (TDI/PCINT21) (PCINT26/RXD1/INT0) PD2 11 23
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This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. 5.2.4.
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6. I/O Multiplexing Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the PORT I/O pins. Table 6-1.
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32-pin TQFP/ QFN/ MLF Pin # 40-pin PDIP Pin # PAD 35 38 36 EXTINT PCINT ADC/AC PA[2] PCINT2 ADC2 39 PA[1] PCINT1 ADC1 37 40 PA[0] PCINT0 ADC0 38 - VCC SDA1 39 - GND SCL1 40 1 PB[0] PCINT8 41 2 PB[1] PCINT9 42 3 PB[2] 43 4 44 INT2 OSC T/C # 0 T/C # 1 T0 CLKO PCINT10 AIN0 PB[3] PCINT11 AIN1 5 PB[4] PCINT12 - - GND - - GND - - GND - - GND - - GND USART I2C SPI JTAG XCK0 T1 OC0A OC0B SS Atmel ATmega644A [DATASHEET] Atmel-42716C-ATmega
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7. General Information 7.1. Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. 7.2. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C. 7.3. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device.
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8. AVR CPU Core 8.1. Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 8-1.
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The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format.
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8.3.1. Status Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. 8.4. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
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Figure 8-3. The X-, Y-, and Z-registers 15 X-register XH 7 0 15 Y-register 7 R26 YH YL 0 7 R28 ZH ZL 0 0 0 R29 7 0 0 R27 7 15 Z-register XL 7 0 0 R31 R30 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 8.5.
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8.5.1. Stack Pointer Register Low and High byte The SPL and SPH register pair represents the 16-bit value, SP.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
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8.5.2. Extended Z-pointer Register for ELPM/SPM When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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8.7. Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. The Figure below shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts: The first type is triggered by an event that sets the Interrupt Flag.
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C Code Example(1) __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 1. Refer to About Code Examples. Related Links Memory Programming on page 362 Boot Loader Support – Read-While-Write Self-Programming on page 345 About Code Examples on page 18 8.8.1. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum.
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9. AVR Memories 9.1. Overview This section describes the different memory types in the device. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the device features an EEPROM Memory for data storage. All memory spaces are linear and regular. 9.2. In-System Reprogrammable Flash Program Memory The ATmega644A contains 64Kbytes On-chip In-System Reprogrammable Flash memory for program storage.
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9.3. SRAM Data Memory The following figure shows how the device SRAM Memory is organized. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 4352 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM.
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Figure 9-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 9.4. Next Instruction EEPROM Data Memory The ATmega644A contains 2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/ erase cycles.
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An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
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For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte is then written into the temporary register. When the high byte of the 16-bit register is written, the temporary register is copied into the low byte of the 16-bit register in the same clock cycle. For a read operation, the low byte of the 16-bit register must be read before the high byte.
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9.6.2. EEPROM Address Register Low and High Byte The EEARL and EEARH register pair represents the 16-bit value, EEAR. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used.
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9.6.3. EEPROM Data Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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9.6.4. EEPROM Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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Bit 1 – EEPE: EEPROM Write Enable The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to '1' to write the value into the EEPROM. The EEMPE bit must be written to '1' before EEPE is written to '1', otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEPE becomes zero. 2.
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Assembly Code Example(1) EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example(1) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
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9.6.5. GPIOR2 – General Purpose I/O Register 2 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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9.6.6. GPIOR1 – General Purpose I/O Register 1 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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9.6.7. GPIOR0 – General Purpose I/O Register 0 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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10. System Clock and Clock Options 10.1. Clock Systems and Their Distribution The following figure illustrates the principal clock systems in the device and their distribution. All the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes. The clock systems are described in the following sections. The system clock frequency refers to the frequency generated from the System Clock Prescaler.
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10.1.1. CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 10.1.2. I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
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10.2.1. Default Clock Source The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock. The startup time is set to maximum, and the time-out period is enabled: CKSEL=0010, SUT=10, CKDIV8=0. This default setting ensures that all users can make their desired clock source setting using any available programming interface. 10.2.2.
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Figure 10-2. Crystal Oscillator Connections C2 XTAL2 C1 XTAL1 GND Related Links Low Power Crystal Oscillator on page 45 Full Swing Crystal Oscillator on page 46 Low Frequency Crystal Oscillator on page 47 10.3. Low Power Crystal Oscillator This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments.
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Table 10-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection Oscillator Source / Power Conditions Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.
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For the Crystall Oscillator connections refer to Low Power Crystal Oscillator. Table 10-6. Start-Up Times for the Full Swing Crystal Oscillator Clock Selection Oscillator Source / Power Conditions Start-Up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT[1:0] Ceramic resonator, fast rising power 258 CK 14CK + 4.
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Table 10-8. Capacitance for Low-Frequency Oscillator 32kHz Osc. Type Cap. (XTAL1/TOSC1) Cap. (XTAL2/TSOC2) System Osc. 18pF 8pF Timer Osc. 6pF 6pF The capacitance (Ce+Ci) needed at each TOSC pin can be calculated by using: �� + �� = 2�� − �� where: • • • • Ce - is optional external capacitors. Ci - is the pin capacitance in the above table. CL - is the load capacitance for a 32.768kHz crystal specified by the crystal vendor. CS - is the total stray capacitance for one TOSC pin.
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This clock may be selected as the system clock by programming the CKSEL Fuses as shown in the following Table. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. By changing the OSCCAL register from SW, it is possible to get a higher calibration accuracy than by using the factory calibration.
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Note: 1. The 128kHz oscillator is a very low power clock source, and is not designed for high accuracy. When this clock source is selected, start-up times are determined by the SUT Fuses: Table 10-13. Start-Up Times for the 128kHz Internal Oscillator Power Conditions Start-Up Time from Power-down and Powersave Additional Delay from Reset SUT[1:0] BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4ms 01 14CK + 65ms 10 Slowly rising power 6 CK Reserved 10.8.
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Power Conditions Start-Up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) SUT[1:0] Slowly rising power 6 CK 14CK + 65ms 10 Reserved 11 When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior.
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source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in the CLKPR description. When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting.
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10.12.1. Oscillator Calibration Register Name: OSCCAL Offset: 0x66 Reset: Device Specific Calibration Value Property: - Bit Access Reset 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:0 – CALn: Oscillator Calibration Value [n = 7:0] The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
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10.12.2. Clock Prescaler Register Name: CLKPR Offset: 0x61 Reset: Refer to the bit description Property: - Bit Access Reset 3 2 1 0 CLKPCE 7 6 5 4 CLKPS3 CLKPS2 CLKPS1 CLKPS0 R/W R/W R/W R/W R/W 0 x x x x Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
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CLKPS[3:0] Clock Division Factor 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Atmel ATmega644A [DATASHEET] Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016 55
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11. PM - Power Management and Sleep Modes 11.1. Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The device provides various sleep modes allowing the user to tailor the power consumption to the application requirements. 11.2. Sleep Modes The following Table shows the different sleep modes and their wake-up sources. Table 11-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
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disable the BOD by software for some of the sleep modes. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe operation in case the VCC level has dropped during the sleep period.
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• • External level interrupt on INT Pin change interrupt Note: 1. Timer/Counter will only keep running in asynchronous mode. Related Links 8-bit Timer/Counter2 with PWM and Asynchronous Operation on page 188 11.6. Power-Down Mode When the SM[2:0] bits are written to '010', the SLEEP instruction makes the MCU enter Power-Down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-wire Serial Interface address watch, and the Watchdog continue operating (if enabled).
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11.8. Standby Mode When the SM[2:0] bits are written to '110' and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-Down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. 11.9.
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Related Links Analog Comparator on page 297 11.11.3. Brown-Out Detector If the Brown-Out Detector (BOD) is not needed by the application, this module should be turned off. If the BOD is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Related Links Brown-out Detection on page 69 11.11.4.
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There are three alternative ways to disable the OCD system: • Disable the OCDEN Fuse • Disable the JTAGEN Fuse • Write one to the JTD bit in MCUCR 11.12.
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11.12.1. Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.
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11.12.2. MCU Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
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11.12.3. Power Reduction Register 0 Name: PRR0 Offset: 0x64 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PRTWI PRTIM2 PRTIM0 PRUSART1 PRTIM1 PRSPI0 PRUSART0 PRADC R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – PRTWI: Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.
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12. SCRST - System Control and Reset 12.1. Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be an Absolute Jump instruction (JMP) to the reset handling routine for . If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
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Figure 12-1. Reset Logic DATA BUS P ORF BORF EXTRF WDRF J TRF MCU S ta tus Re gis te r (MCUS R) Powe r-on Re s e t Circuit Brown-out Re s e t Circuit BODLEVEL [2..0] P ull-up Re s is tor S P IKE FILTER J TAG Re s e t Re gis te r Wa tchdog Os cilla tor Clock Ge ne ra tor CK De lay Counte rs TIMEOUT CKS EL[3:0] S UT[1:0] Related Links IEEE 1149.1 (JTAG) Boundary-scan on page 331 12.3. Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit.
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Figure 12-3. MCU Start-up, RESET Extended Externally VCC VPOT RESET TIME-OUT VRST tTOUT INTERNAL RESET 12.4. External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
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Figure 12-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET t TOUT TIME-OUT INTERNAL RESET 12.6. Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Figure 12-6. Watchdog System Reset During Operation CC CK 12.7. Internal Voltage Reference The device features an internal bandgap reference.
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12.8. Watchdog Timer If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Watchdog System Reset for details on how to configure the watchdog timer. Features • • • • 12.8.2.
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The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows: 1.
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The following code examples shows how to change the time-out value of the Watchdog Timer. Assembly Code Example WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR ori r16, (1<
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12.9.1. MCU Status Register To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used.
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12.9.2. WDTCSR – Watchdog Timer Control Register Name: WDTCSR Offset: 0x60 Reset: 0x00 Property: Bit Access Reset 7 6 5 4 3 WDIF WDIE WDP[3] WDCE WDE 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 WDP[2:0] Bit 7 – WDIF: Watchdog Interrupt Flag This bit is set when a timeout occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
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Bit 3 – WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Bits 2:0 – WDP[2:0]: Watchdog Timer Prescaler 2, 1, and 0 The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.
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13. Interrupts 13.1. Overview This section describes the specifics of the interrupt handling of the device. For a general explanation of the AVR interrupt handling, refer to the description of Reset and Interrupt Handling. In general: • Each Interrupt Vector occupies two instruction words. • The Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR (MCUCR.IVSEL) Related Links Reset and Interrupt Handling on page 26 13.2.
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Vector No Program Address(2) Source Interrupts definition 21 0x0028 USART_RX USART Rx Complete 22 0x002A USART_UDRE USART Data Register Empty 23 0x002C USART_TX USART Tx Complete 24 0x002E ANALOG_COMP Analog Comparator 25 0x0030 ADC ADC Conversion Complete 26 0x0032 EE_READY EEPROM Ready 27 0x0034 TWI TWI Transfer complete 28 0x0036 SPM_READY Store Program Memory Ready 29 0x0038 USART1_RX USART1 Rx Complete 30 0x003A USART1_UDRE USART1, Data Register Empty 31 0x003C
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0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 0x0034 0x0036 0x0038 0x003A 0x003C ; 0x003E 0x003F 0x0040 0x0041 0x0042 0x0043 ... RESET: ... jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_COMPA TIM0_COMPB TIM0_OVF SPI_STC USART_RXC USART_UDRE USART_TXC ANA_COMP ADC EE_RDY TWI SPM_RDY USART1_RXC USART1_UDRE USART1_TXC ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ldi out ldi out sei ...
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0x1F004 ... 0x1F036 ; 0x1F03E 0x1F03F 0x1F040 0x1F041 0x1F042 0x1FO43 RESET: jmp ... jmp EXT_INT1 ... SPM_RDY ; IRQ1 Handler ; ; SPM Ready Handler ldi out ldi out sei r16,high(RAMEND) SPH,r16 r16,low(RAMEND) SPL,r16 ; Main program start ; Set Stack Pointer to top of RAM xxx ; Enable interrupts 13.3. Register Description 13.3.1. Moving Interrupts Between Application and Boot Space The MCU Control Register controls the placement of the Interrupt Vector table.
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13.3.2. MCU Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
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14. External Interrupts 14.1. EXINT - External Interrupts The External Interrupts are triggered by the INT pin or any of the PCINT pins. Observe that, if enabled, the interrupts will trigger even if the INT or PCINT pins are configured as outputs. This feature provides a way of generating a software interrupt. The Pin Change Interrupt Request 3 (PCI3) will trigger if any enabled PCINT[31:24] pin toggles. The Pin Change Interrupt Request 2 (PCI2) will trigger if any enabled PCINT[23:16] pin toggles.
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Figure 14-1. Timing of pin change interrupts 0 PCINT[i] pin D Q pin_lat D Q pin_sync LE PCINT[i] bit (of PCMSKn) clk pcint_sync pcint_in[i] D Q pcint_set/flag D Q D 7 Q PCIFn (interrupt flag) clk clk PCINT[i] pin pin_lat pin_sync pcint_in[i] pcint_syn pcint_set/flag PCIFn 14.1.2.
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14.1.2.1. External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Name: EICRA Offset: 0x69 Reset: 0x00 Property: - Bit 7 Access Reset 6 5 4 3 2 1 0 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 5:4 – ISC2n: Interrupt Sense Control 2 [n = 1:0] The External Interrupt 2 is activated by the external pin INT2 if the SREG I-flag and the corresponding interrupt mask are set.
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Value 00 01 10 11 Description The low level of INT0 generates an interrupt request. Any logical change on INT0 generates an interrupt request. The falling edge of INT0 generates an interrupt request. The rising edge of INT0 generates an interrupt request.
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14.1.2.2. External Interrupt Mask Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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14.1.2.3. External Interrupt Flag Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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14.1.2.4. Pin Change Interrupt Control Register Name: PCICR Offset: 0x68 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PCIE3 PCIE2 PCIE1 PCIE0 R/W R/W R/W R/W 0 0 0 0 Bit 3 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 3 is enabled. Any change on any enabled PCINT[31:24] pin will cause an interrupt.
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14.1.2.5. Pin Change Interrupt Flag Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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14.1.2.6. Pin Change Mask Register 0 Name: PCMSK0 Offset: 0x6B Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – PCINTn: Pin Change Enable Mask [n = 7:0] Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
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14.1.2.7. Pin Change Mask Register 1 Name: PCMSK1 Offset: 0x6C Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT8, PCINT9, PCINT10, PCINT11, PCINT12, PCINT13, PCINT14, PCINT15: Pin Change Enable Mask Each PCINT[15:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
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14.1.2.8. Pin Change Mask Register 2 Name: PCMSK2 Offset: 0x6D Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT16, PCINT17, PCINT18, PCINT19, PCINT20, PCINT21, PCINT22, PCINT23: Pin Change Enable Mask Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
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14.1.2.9. Pin Change Mask Register 3 Name: PCMSK3 Offset: 0x73 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PCINT31 PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT24, PCINT25, PCINT26, PCINT27, PCINT28, PCINT29, PCINT30, PCINT31: Pin Change Enable Mask Each PCINT[31:24]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
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15. I/O-Ports 15.1. Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
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15.2. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. The following figure shows the functional description of one I/O-port pin, here generically called Pxn. Figure 15-2.
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15.2.2. Toggling the Pin Writing a '1' to PINxn toggles the value of PORTxn, independent on the value of DDRxn. The SBI instruction can be used to toggle one single bit in a port. 15.2.3. Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
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region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in the following figure.
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i = PINB; ... 15.2.5. Digital Input Enable and Sleep Modes As shown in the figure of General Digital I/O, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins.
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Figure 15-5.
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Table 15-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
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Port Pin Alternate Functions PA5 ADC5 (ADC input channel 5) PCINT5 (Pin Change Interrupt 5) PA4 ADC4 (ADC input channel 4) PCINT4 (Pin Change Interrupt 4) PA3 ADC3 (ADC input channel 3) PCINT3 (Pin Change Interrupt 3) PA2 ADC2 (ADC input channel 2) PCINT2 (Pin Change Interrupt 2) PA1 ADC1 (ADC input channel 1) PCINT1 (Pin Change Interrupt 1) PA0 ADC0 (ADC input channel 0) PCINT0 (Pin Change Interrupt 0) The alternate pin configuration is as follows: • ADC[7:0]/PCINT[7:0] – Port A, Bit [7:0] – A
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Table 15-5. Overriding Signals for Alternate Functions in PA3...
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Port Pin Alternate Functions PB1 T1 (Timer/Counter 1 External Counter Input) CLKO (Divided System Clock Output) PCINT9 (Pin Change Interrupt 9) PB0 T0 (Timer/Counter 0 External Counter Input) XCK0 (USART0 External Clock Input/Output) PCINT8 (Pin Change Interrupt 8) The alternate pin configuration is as follows: • SCK/PCINT15 – Port B, Bit 7 – SCK: Master Clock output, Slave Clock input pin for SPI0 channel.
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– – OC0A: Output Compare Match A output. The PB3 pin can serve as an external output for the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB3 set “1”) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function. PCINT11: Pin Change Interrupt source 11. The PB3 pin can serve as an external interrupt source. • AIN0/INT2/PCINT10 – Port B, Bit 2 – AIN0: Analog Comparator Positive input.
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Signal Name PB7/SCK/PCINT15 PB6/MISO/PCINT14 PB5/MOSI/PCINT13 PB4/SS/OC0B/PCINT12 DI SCK INPUT PCINT15 INPUT SPI MSTR INPUT PCINT14 INPUT SPI SLAVE INPUT PCINT13 INPUT SPI SS PCINT12 INPUT AIO - - – – Table 15-8.
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Port Pin Alternate Function PC3 TMS (JTAG Test Mode Select) PCINT19 (Pin Change Interrupt 19) PC2 TCK (JTAG Test Clock) PCINT18 (Pin Change Interrupt 18) PC1 SDA (two-wire Serial Bus Data Input/Output Line) PCINT17 (Pin Change Interrupt 17) PC0 SCL (two-wire Serial Bus Clock Line) PCINT16 (Pin Change Interrupt 16) The alternate pin configuration is as follows: • TOSC2/PCINT23 – Port C, Bit 7 – TOSC2: Timer Oscillator pin 2. The PC7 pin can serve as an external interrupt source to the MCU.
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• SCL/PCINT16 – Port C, Bit 0 – SCL: two-wire Serial Bus Clock Line. – PCINT16: Pin Change Interrupt source 16. The PC0 pin can serve as an external interrupt source. The tables below relate the alternate functions of Port C to the overriding signals shown in Figure 15-5. Table 15-10.
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Table 15-12.
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– PCINT30: Pin Change Interrupt source 30. The PD6 pin can serve as an external interrupt source. • OC1A/PCINT29 – Port D, Bit 5 – OC1A: Output Compare Match output. The PD5 pin can serve as an external output for the Timer/Counter1 Compare Match A. The PD5 pin has to be configured as an output (DDD5 set '1') to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. – PCINT29: Pin Change Interrupt source 29. The PD5 pin can serve as an external interrupt source.
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Table 15-13. Overriding Signals for Alternate Functions PD[7:4] Signal PD7/OC2A/PCINT31 PD6/ICP1/OC2B/PCINT30 Name PD5/OC1A/PCINT29 PD4/OC1B/XCK1/PCINT28 PUOE 0 0 0 0 PUO 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE OC2A ENABLE OC2B ENABLE OC1A ENABLE OC1B ENABLE PVOV OC2A OC2B OC1A OC1B DIEOE PCINT31 • PCIE3 PCINT30 • PCIE3 PCINT29 • PCIE3 PCINT28 • PCIE3 DIEOV 1 1 1 1 DI ICP1 INPUT PCINT29 INPUT PCINT28 INPUT – – PCINT31 INPUT PCINT30 INPUT AIO - - Table 15-14.
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1. 15.4. When enabled, the two-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module.
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15.4.1. MCU Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
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15.4.2. Port A Data Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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15.4.3. Port A Data Direction Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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15.4.4. Port A Input Pins Address When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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15.4.5. Port B Data Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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15.4.6. Port B Data Direction Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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15.4.7. Port B Input Pins Address When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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15.4.8. Port C Data Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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15.4.9. Port C Data Direction Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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15.4.10. Port C Input Pins Address When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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15.4.11. Port D Data Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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15.4.12. Port D Data Direction Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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15.4.13. Port D Input Pins Address When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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16. TC0 - 8-bit Timer/Counter0 with PWM Related Links Timer/Counter0 and Timer/Counter1 Prescalers on page 185 16.1. Features • • • • • • • 16.2.
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Figure 16-1. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic Clock Select clkTn Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn =0 = OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA Fixed TOP Value Waveform Generation = OCnB OCRnB TCCRnA 16.2.1. OCnB (Int.Req.
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Table 16-1. Definitions Constant Description BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00 for 8-bit counters, or 0x0000 for 16-bit counters). 16.2.2. MAX The counter reaches its Maximum when it becomes 0xFF (decimal 255, for 8-bit counters) or 0xFFFF (decimal 65535, for 16-bit counters). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value MAX or the value stored in the OCR0A Register.
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Figure 16-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count clear TCNTn direction Control Logic Edge Detector clkTn Tn ( From Prescaler ) bottom top Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B). Table 16-2. Signal description (internal signals) Signal Name Description count Increment or decrement TCNT0 by 1. direction Select between increment and decrement.
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mode (COM0x[1:0]) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation. Figure 16-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn[1:0] COMnx[1:0] Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B).
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compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the TCCR0A.
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by the Data Direction Register (DDR) for the port pin. In the Data Direction Register, the bit for the OC1x pin (DDR.OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x register state before the output is enabled. Some TCCR0A.COM0x[1:0] bit settings are reserved for certain modes of operation. The TCCR0A.
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16.7.2. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM0[2:0]=0x2), the OCR0A Register is used to manipulate the counter resolution: the counter is cleared to ZERO when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the counting of external events. The timing diagram for the CTC mode is shown below.
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frequency of the Fast PWM mode can be twice as high as the phase correct PWM modes, which use dual-slope operation. This high frequency makes the Fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In Fast PWM mode, the counter is incremented until the counter value matches the TOP value.
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A frequency waveform output with 50% duty cycle can be achieved in Fast PWM mode by selecting OC0x to toggle its logical level on each compare match (COM0x[1:0]=0x1). The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A=0x00. This feature is similar to the OC0A toggle in CTC mode, except double buffering of the Output Compare unit is enabled in the Fast PWM mode. 16.7.4.
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set. This option is not available for the OC0B pin. The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0x Register at the compare match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at compare match between OCR0x and TCNT0 when the counter decrements.
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Figure 16-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B). The next figure shows the setting of OCF0B in all modes and OCF0A in all modes (except CTC mode and PWM mode where OCR0A is TOP). Figure 16-10.
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Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B). 16.9.
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16.9.1. TC0 Control Register A When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details. The table below shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode. Table 16-5. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected.
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Table 16-7. Compare Output Mode, Fast PWM(1) COM0B1 COM0B0 Description 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match, set OC0B at BOTTOM, (non-inverting mode) 1 1 Set OC0B on Compare Match, clear OC0B at BOTTOM, (inverting mode) Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. Refer to Fast PWM Mode for details.
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1. 2.
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16.9.2. TC0 Control Register B When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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Table 16-10. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
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16.9.3. TC0 Interrupt Mask Register Name: TIMSK0 Offset: 0x6E Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 OCIEB OCIEA TOIE R/W R/W R/W 0 0 0 Bit 2 – OCIEB: Timer/Counter0, Output Compare B Match Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in TIFR0.
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16.9.4. General Timer/Counter Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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16.9.5. TC0 Counter Value Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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16.9.6. TC0 Output Compare Register A When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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16.9.7. TC0 Output Compare Register B When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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16.9.8. TC0 Interrupt Flag Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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17. TC1 - 16-bit Timer/Counter1 with PWM Related Links Timer/Counter0 and Timer/Counter1 Prescalers on page 185 17.1. Overview The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. A block diagram of the 16-bit Timer/Counter is shown below. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in Register Description.
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Figure 17-1. 16-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic Clock Select clkTn Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA TCCRnB See the related links for actual pin placement. 17.4.
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Table 17-1. Definitions Constant Description BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00 for 8-bit counters, or 0x0000 for 16-bit counters). 17.5. MAX The counter reaches its Maximum when it becomes 0xFF (decimal 255, for 8-bit counters) or 0xFFFF (decimal 65535, for 16-bit counters). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value MAX or the value stored in the OCR1A Register.
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Accessing the low byte triggers the 16-bit read or write operation: When the low byte of a 16-bit register is written by the CPU, the high byte that is currently stored in TEMP and the low byte being written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the TEMP register in the same clock cycle as the low byte is read, and must be read subsequently.
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Assembly Code Example(1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret The assembly code example returns the TCNT1 value in the r17:r16 register pair.
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} /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
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Table 17-2. Signal description (internal signals) Signal Name Description Count Increment or decrement TCNT1 by 1. Direction Select between increment and decrement. Clear Clear TCNT1 (set all bits to zero). clkT1 Timer/Counter clock. TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero).
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Figure 17-3. Input Capture Unit Block Diagram for TC1 DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) ACO Analog Comparator TCNTnL (8-bit) TCNTn (16-bit Counter) ACIC ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.) ICPn Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B).
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the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin. The edge detector is also identical.
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bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation, see Modes of Operation. A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Below is a block diagram of the Output Compare unit.
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copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to Accessing 16-bit Timer/Counter Registers. 17.10.1. Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (TCCR1C.FOC1x) bit.
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Figure 17-5. Compare Match Output Unit, Schematic COMnx[1] COMnx[0] FOCnx Waveform Generator D Q 1 OCnx DATA BUS D OCnx Pin 0 Q PORT D Q DDR clk I/O Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the TCCR1A.COM1x[1:0] bits are set.
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Related Links Timer/Counter Timing Diagrams on page 171 Compare Match Output Unit on page 162 17.12.1. Normal Mode The simplest mode of operation is the Normal mode (TCCR1A.WGM1[3:0]=0x0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX=0xFFFF) and then restarts from BOTTOM=0x0000. In normal operation the Timer/Counter Overflow Flag (TIFR1.
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An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag, depending on the actual CTC mode. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. Note: Changing TOP to a value close to BOTTOM while the counter is running must be done with care, since the CTC mode does not provide double buffering.
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TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT1 slopes mark compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 17-7.
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In Fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Writing the COM1x[1:0] bits to 0x2 will produce an inverted PWM and a non-inverted PWM output can be generated by writing the COM1x[1:0] to 0x3. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x).
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diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT1 slopes mark compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 17-8.
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the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements.
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Figure 17-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx[1:0] = 0x2) OCnx (COMnx[1:0] = 0x3) Period 1 2 3 4 Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B).
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Note: • The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). • N represents the prescale divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode.
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Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The next figure shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 17-12.
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17.14.1. TC1 Control Register A Name: TCCR1A Offset: 0x80 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 1 0 COM1 COM1 COM1 COM1 3 2 WGM11 WGM10 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 4, 5, 6, 7 – COM1, COM1, COM1, COM1: Compare Output Mode for Channel The COM1A[1:0] and COM1B[1:0] control the Output Compare pins (OC1A and OC1B respectively) behavior.
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COM1A1/ COM1B1 COM1A0/ COM1B0 Description 1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM (non-inverting mode) 1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM (inverting mode) Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details.
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Mode WGM13 WGM12 WGM11 WGM10 (CTC1)(1) (PWM11)(1) (PWM10)(1) Timer/ Counter TOP Update of TOV1 Flag OCR1x at Set on Mode of Operation 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 5 0 1 0 0 CTC OCR1A Immediate MAX 1 Fast PWM, 8bit 0x00FF BOTTOM TOP 6 0 1 1 0 Fast PWM, 9bit 0x01FF BOTTOM TOP 7 0 1 1 1 Fast PWM, 10bit 0x03FF BOTTOM TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and
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17.14.2. TC1 Control Register B Name: TCCR1B Offset: 0x81 Reset: 0x00 Property: - Bit Access 7 6 4 3 2 1 0 ICNC1 ICES1 WGM13 WGM12 CS12 CS11 CS10 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Reset 5 Bit 7 – ICNC1: Input Capture Noise Canceler Writing this bit to '1' activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered.
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CS12 CS11 CS10 Description 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge.
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17.14.3. TC1 Control Register C Name: TCCR1C Offset: 0x82 Reset: 0x00 Property: - Bit Access Reset 7 6 FOC1A FOC1B R/W R/W 0 0 5 4 3 2 1 0 Bit 7 – FOC1A: Force Output Compare for Channel A Bit 6 – FOC1B: Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the WGM1[3:0] bits specifies a non-PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
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17.14.4. TC1 Counter Value Low and High byte The TCNT1L and TCNT1H register pair represents the 16-bit value, TCNT1.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
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17.14.5. Input Capture Register 1 Low and High byte The ICR1L and ICR1H register pair represents the 16-bit value, ICR1.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
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17.14.6. Output Compare Register 1 A Low and High byte The OCR1AL and OCR1AH register pair represents the 16-bit value, OCR1A.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
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17.14.7. Output Compare Register 1 B Low and High byte The OCR1BL and OCR1BH register pair represents the 16-bit value, OCR1B.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
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17.14.8. Timer/Counter 1 Interrupt Mask Register Name: TIMSK1 Offset: 0x6F Reset: 0x00 Property: - Bit Access Reset 7 6 2 1 0 ICIE 5 4 3 OCIEB OCIEA TOIE R/W R/W R/W R/W 0 0 0 0 Bit 5 – ICIE: Input Capture Interrupt Enable When this bit is written to '1', and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector is executed when the ICF Flag, located in TIFR1, is set.
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17.14.9. TC1 Interrupt Flag Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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18. Timer/Counter 0, 1 Prescalers The 8-bit Timer/Counter0 (TC0) , 16-bit Timer/Counters 1 (TC1) share the same prescaler module, but the Timer/Counters can have different prescaler settings. The following description applies to: TC0 , TC1 . Related Links 8-bit Timer/Counter0 with PWM on page 127 16-bit Timer/Counter1 with PWM on page 152 18.1. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0]=0x1).
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The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling.
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18.4.1. General Timer/Counter Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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19. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation 19.1. Features • • • • • • • 19.2.
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Figure 19-1. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic Clock Select clkTn Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) Waveform Generation = OCnA OCRnA DATA BUS Fixed TOP Value OCnB (Int.Req.) Waveform Generation = OCnB OCRnB TCCRnA TCCRnB Related Links Pin Configurations on page 13 Pin Descriptions on page 14 19.2.1.
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Table 19-1. Definitions Constant Description BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). 19.2.2. MAX The counter reaches its maximum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The assignment is dependent on the mode of operation.
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Figure 19-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count clear TCNTn clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 clkI/O top Table 19-2. Signal description (internal signals): Signal name Description count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following.
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Figure 19-3. Output Compare Unit, Block Diagram DATA BUS TCNTn OCRnx = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn[1:0] COMnx[1:0] The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting sequence.
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compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when changing between Waveform Generation modes.
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19.6.1. Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x[1:0] bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x[1:0] = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on the next compare match. Refer also to the descriptions of the output modes. A change of the COM2x[1:0] bits state will have effect at the first compare match after the bits are written.
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Figure 19-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) (COMnx[1:0] = 0x1) Period 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
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small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 19-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCnx (COMnx[1:0] = 0x2) OCnx (COMnx[1:0] = 0x3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
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0xFF when WGM2[2:0] = 0x3, and OCR2A when MGM2[2:0] = 7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation.
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�OCnxPCPWM = �clk_I/O � ⋅ 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
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Figure 19-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn The following figure shows the setting of OCF2A in all modes except CTC mode. Figure 19-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx The following figure shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
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• • • • • • • 1. Disable the TC2 interrupts by clearing OCIE2x and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2x, and TCCR2x. 4. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB. 5. Clear the TC2 Interrupt Flags. 6. Enable interrupts, if needed. The CPU main clock frequency must be more than four times the oscillator frequency.
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• unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1. Wait for the corresponding Update Busy Flag to be cleared. 2. Read TCNT2. During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag.
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19.11.1. TC2 Control Register A Name: TCCR2A Offset: 0xB0 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 COM2A1 COM2A0 COM2B1 R/W R/W R/W 0 0 0 3 2 1 0 COM2B0 WGM21 WGM20 R/W R/W R/W 0 0 0 Bits 7:6 – COM2An: Compare Output Mode for Channel A [n = 1:0] These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A[1:0] bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to.
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Table 19-5. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Match when down-counting. 1 1 Set OC2A on Compare Match when up-counting. Clear OC2A on Compare Match when down-counting. Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set.
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1. A special case occurs when OCR2B equals TOP and COM2B[1] is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. Refer to Fast PWM Mode for details. The table below shows the COM2B[1:0] bit functionality when the WGM2[2:0] bits are set to phase correct PWM mode. Table 19-8. Compare Output Mode, Phase Correct PWM Mode(1) COM2B1 COM2B0 Description 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on Compare Match when up-counting.
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19.11.2. TC2 Control Register B Name: TCCR2B Offset: 0xB1 Reset: 0x00 Property: - Bit Access Reset 7 6 FOC2A FOC2B 5 4 WGM22 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 CS2[2:0] Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. To ensure compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
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CA22 CA21 CS20 Description 0 1 1 clkI/O/32 (From prescaler) 1 0 0 clkI/O/64 (From prescaler) 1 0 1 clkI/O/128 (From prescaler) 1 1 0 clkI/O/256 (From prescaler) 1 1 1 clkI/O/1024 (From prescaler) If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.
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19.11.3. TC2 Counter Value Register Name: TCNT2 Offset: 0xB2 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 TCNT2[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TCNT2[7:0]: Timer/Counter 2 Counter Value The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock.
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19.11.4. TC2 Output Compare Register A Name: OCR2A Offset: 0xB3 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 OCR2A[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR2A[7:0]: Output Compare 2 A The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2A pin.
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19.11.5. TC2 Output Compare Register B Name: OCR2B Offset: 0xB4 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 OCR2B[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR2B[7:0]: Output Compare 2 B The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2B pin.
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19.11.6. TC2 Interrupt Mask Register Name: TIMSK2 Offset: 0x70 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 OCIEB OCIEA TOIE R/W R/W R/W 0 0 0 Bit 2 – OCIEB: Timer/Counter2, Output Compare B Match Interrupt Enable When the OCIEB bit is written to '1' and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e.
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19.11.7. TC2 Interrupt Flag Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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19.11.8. Asynchronous Status Register Name: ASSR Offset: 0xB6 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB Access R R R R R R R Reset 0 0 0 0 0 0 0 Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal.
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19.11.9. General Timer/Counter Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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20. SPI – Serial Peripheral Interface 20.1. Features • • • • • • • • 20.2. Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral units, or between several AVR devices.
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Figure 20-1. SPI Block Diagram SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128 Note: Refer to the pin-out description and the IO Port description for SPI pin placement. The interconnection between Master and Slave CPUs with SPI is shown in the figure below. The system consists of two shift registers, and a Master Clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave.
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data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 20-2. SPI Master-slave Interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed.
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SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait for transmission complete in r16, SPSR sbrs r16, SPIF rjmp Wait_Transmit ret C Code Example void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<
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Pin Descriptions on page 14 USARTSPI - USART in SPI Mode on page 252 PM - Power Management and Sleep Modes on page 56 I/O-Ports on page 95 About Code Examples on page 18 20.3. SS Pin Functionality 20.3.1. Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs.
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SPI Mode Conditions Leading Edge Trailing Edge 2 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 3 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) The SPI data transfer formats are shown in the following figure. Figure 20-3.
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20.5.1. SPI Control Register 0 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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Table 20-4. CPHA0 Functionality CPHA0 Leading Edge Trailing Edge 0 Sample Setup 1 Setup Sample Bits 1:0 – SPR0n: SPI0 Clock Rate Select n [n = 1:0] These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the table below. Table 20-5.
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20.5.2. SPI Status Register 0 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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20.5.3. SPI Data Register 0 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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21. USART - Universal Synchronous Asynchronous Receiver Transceiver 21.1. Features • • • • • • • • • • • • • 21.2.
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Figure 21-1. USART Block Diagram Clock Generator UBRRn [H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCKn Transmitter TX CONTROL DATA BUS UDRn(Transmit) PARITY GENERATOR PIN CONTROL TRANSMIT SHIFT REGISTER TxDn Receiver UCSRnA CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDRn (Receive) PARITY CHECKER UCSRnB RxDn UCSRnC Note: Refer to the Pin Configurations and the I/O-Ports description for USART pin placement. 21.4.
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Figure 21-2. Clock Generation Logic, Block Diagram UBRRn U2Xn fosc Prescaling Down-Counter UBRRn+1 /2 /4 /2 0 1 0 OSC 1 DDR_XCKn xcki XCKn Pin Sync Register Edge Detector xcko DDR_XCKn 0 txclk UMSELn 1 UCPOLn 1 0 rxclk Signal description: 21.4.1. • • • txclk: Transmitter clock (internal signal). rxclk: Receiver base clock (internal signal). xcki: Input from XCKn pin (internal signal). Used for synchronous slave operation. • • xcko: Clock output to XCKn pin (internal signal).
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BAUD Baud rate (in bits per second, bps) fOSC System oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095). Some examples of UBRRn values for some system clock frequencies are found in Examples of Baud Rate Settings. 21.4.2. Double Speed Operation (U2X) The transfer rate can be doubled by setting the U2X bit in UCSRnA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
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rising XCKn edge and sampled at falling XCKn edge. If UCPOL is set, the data will be changed at falling XCKn edge and sampled at rising XCKn edge. 21.5. Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking.
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dn Data bit n of the character If used, the parity bit is located between the last data bit and first stop bit of a serial frame. 21.6. USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage.
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code can be placed directly in the main routine, or be combined with initialization code for other I/O modules. Related Links About Code Examples on page 18 21.7. Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden by the USART and given the function as the Transmitter’s serial output.
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21.7.2. Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The ninth bit can be used for indicating an address frame when using multi processor communication mode or for other protocol handling as for example synchronization. The following code examples show a transmit function that handles 9-bit characters.
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The Transmit Complete (TXC) Flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC Flag bit is either automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a '1' to its bit location.
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C Code Example unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSR0A & (1<
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} /* from buffer */ status = UCSR0A; resh = UCSR0B; resl = UDR0; /* If error, return -1 */ if ( status & (1<> 1) & 0x01; return ((resh << 8) | resl); The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible.
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The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPE bit will always read '0'. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see Parity Bit Calculation and 'Parity Checker' below. 21.8.5. Parity Checker The Parity Checker is active when the high USART Parity Mode bit 1 in the USART Control and Status Register n C (UCSRnC.UPM[1]) is written to '1'.
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filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 21.9.1. Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. The figure below illustrates the sampling process of the start bit of an incoming frame.
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The following figure shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 21-7. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample 1 (U2X = 0) 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample 1 (U2X = 1) 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic '0' value, the Frame Error (UCSRnA.FE) Flag will be set.
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D # (Data+Parity Bit) Rslow [%] Rfast [%] Max. Total Error [%] Recommended Max. Receiver Error [%] 7 94.81 105.11 +5.11/-5.19 ±2.0 8 95.36 104.58 +4.58/-4.54 ±2.0 9 95.81 104.14 +4.14/-4.19 ±1.5 10 96.17 103.78 +3.78/-3.83 ±1.5 Table 21-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) D # (Data+Parity Bit) Rslow [%] Rfast [%] Max Total Error [%] Recommended Max Receiver Error [%] 5 94.12 105.66 +5.66/-5.88 ±2.5 6 94.92 104.92 +4.92/-5.
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particular slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. 21.10.1. Using MPCMn For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ1=7). The ninth bit (TXB8) must be set when an address frame (TXB8=1) or cleared when a data frame (TXB=0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character frame format.
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Baud Rate [bps] fosc = 1.0000MHz fosc = 1.8432MHz fosc = 2.0000MHz U2X = 0 U2X = 1 U2X = 0 U2X = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.
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Baud Rate [bps] fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz U2X = 0 U2X = 0 U2X = 0 U2X = 1 U2X = 1 U2X = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 1M – – Max.(1) 230.4kbps – – 460.8kbps – – 250kbps – – – 0.5Mbps – 460.8kbps 0 -7.8% 921.6kbps (1) UBRRn = 0, Error = 0.0% Table 21-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies Baud Rate [bps] fosc = 8.0000MHz fosc = 11.0592MHz fosc = 14.
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Baud Rate [bps] fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz U2X = 0 U2X = 0 U2X = 0 U2X = 1 U2X = 1 U2X = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.
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21.12.1. USART I/O Data Register n The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR1 Register location. Reading the UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).
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21.12.2. USART Control and Status Register n A Name: UCSR0A, UCSR1A Offset: 0xC0 + n*0x08 [n=0..1] Reset: 0x20 Property: - Bit 7 6 5 4 3 2 1 0 RXC TXC UDRE FE DOR UPE U2X MPCM Access R R/W R R R R R/W R/W Reset 0 0 1 0 0 0 0 0 Bit 7 – RXC: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data).
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Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. This bit is reserved in Master SPI Mode (MSPIM). Bit 0 – MPCM: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode.
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21.12.3. USART Control and Status Register n B Name: UCSR0B, UCSR1B Offset: 0xC1 + n*0x08 [n=0..1] Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 R/W R/W R/W R/W R/W R/W R R/W 0 0 0 0 0 0 0 0 Bit 7 – RXCIE: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the UCSRnA.RXC Flag.
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Bit 0 – TXB8: Transmit Data Bit 8 TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDRn. This bit is reserved in Master SPI Mode (MSPIM).
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21.12.4. USART Control and Status Register n C Name: UCSR0C, UCSR1C Offset: 0xC2 + n*0x08 [n=0..1] Reset: 0x06 Property: - Bit 7 6 5 UMSEL[1:0] Access Reset 4 UPM[1:0] 3 2 1 0 USBS UCSZ1 / UCSZ0 / UCPOL UDORD UCPHA R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 1 0 Bits 7:6 – UMSEL[1:0]: USART Mode Select These bits select the mode of operation of the USARTn Table 21-8.
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Table 21-10. Stop Bit Settings USBS Stop Bit(s) 0 1-bit 1 2-bit This bit is reserved in Master SPI Mode (MSPIM). Bit 2 – UCSZ1 / UDORD: USART Character Size / Data Order UCSZ1[1:0]: USART Modes: The UCSZ1[1:0] bits combined with the UCSZ12 bit in UCSR1B sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use. Table 21-11.
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Master SPI Mode: The UCPOL bit sets the polarity of the XCKn clock. The combination of the UCPOL and UCPHA bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and Timing for details.
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21.12.5. USART Baud Rate n Register Low and High byte The UBRRnL and UBRRnH register pair represents the 16-bit value, UBRRn (n=0,1).The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. Name: UBRR0L and UBRR0H, UBRR1L and UBRR1H Offset: 0xC4 + n*0x08 [n=0..
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22. USARTSPI - USART in SPI Mode 22.1. Features • • • • • • • • 22.2.
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22.4. BAUD Baud rate (in bits per second, bps) fOSC System Oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095) SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in the following figure.
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The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. 16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit complete interrupt will then signal that the 16-bit value has been shifted out. 22.5.1.
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/* IMPORTANT: The Baud Rate must be set after the transmitter is enabled */ UBRRn = baud; } Related Links About Code Examples on page 18 22.6. Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the Transmitter's serial output.
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C Code Example { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
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22.8. USART_MSPIM SPI Comments XCKn SCK (Functionally identical) (N/A) SS Not supported by USART in MSPIM Register Description Refer to the USART Register Description.
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23. TWI - 2-wire Serial Interface 23.1. Features • • • • • • • • • • • 23.2.
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Table 23-1. TWI Terminology Term Description Master The device that initiates and terminates a transmission. The Master also generates the SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus. This device has one instance of TWI. For this reason, the instance index n is omitted. The Power Reduction TWI bit in the Power Reduction Register (PRRn.
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23.3.2. START and STOP Conditions The Master initiates and terminates a data transmission. The transmission is initiated when the Master issues a START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. A special case occurs when a new START condition is issued between a START and STOP condition.
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Figure 23-4. Address Packet Format Addr MSB Addr LSB R/W ACK 7 8 9 SD A SCL 1 2 START 23.3.4. Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle.
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Figure 23-6. Typical Data Transmission Addr MSB Addr LSB R/W ACK Data MSB 7 8 9 1 Data LSB ACK 8 9 SD A SCL 1 START 23.4. 2 SLA+R/W 2 7 Data Byte ST OP Multi-master Bus Systems, Arbitration, and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time.
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Figure 23-7. SCL Synchronization Between Multiple Masters TAlow TAhigh SCL from Master A TBlow TBhigh SCL from Master B SCL Bus Line Masters Start Counting Low Period Masters Start Counting High Period Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the Master had output, it has lost the arbitration.
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data packets. In other words; All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 23.5. Overview of the TWI Module The TWI module is comprised of several submodules, as shown in the following figure. The registers drawn in a thick line are accessible through the AVR data bus. Figure 23-9.
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(TWSRn). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period.
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The TWINT Flag is set in the following situations: After the TWI has transmitted a START/REPEATED START condition After the TWI has transmitted SLA+R/W After the TWI has transmitted an address byte After the TWI has lost arbitration After the TWI has been addressed by own slave address or general call After the TWI has received a data byte After a STOP or REPEATED START has been received while still addressed as a Slave • When a bus error has occurred due to an illegal START or STOP condition Using the T
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2. 3. 4. 5. 6. 7. TWINT bit in TWCRn is set. Immediately after the application has cleared TWINT, the TWI n will initiate transmission of the START condition. When the START condition has been transmitted, the TWINT Flag in TWCRn is set, and TWSRn is updated with a status code indicating that the START condition has successfully been sent. The application software should now examine the value of TWSRn, to make sure that the START condition was successfully transmitted.
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TWINT clears the flag. The TWI n will then commence executing whatever operation was specified by the TWCRn setting. The following table lists assembly and C implementation examples for TWI0. Note that the code below assumes that several definitions have been made, e.g. by using include-files. Table 23-2.
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Assembly Code Example 7 C Example in r16,TWSR0 andi r16, 0xF8 cpi r16, MT_DATA_ACK brne ERROR if ((TWSR0 & 0xF8) != MT_DATA_ACK) ERROR(); ldi r16, (1<
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23.7.1. Master Transmitter Mode In the Master Transmitter (MT) mode, a number of data bytes are transmitted to a Slave Receiver, see figure below. In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether MT or Master Receiver (MR) mode is to be entered: If SLA +W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
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to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 23-3.
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Status Code (TWSR) Prescaler Bits are 0 0x28 0x30 0x38 Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Data byte has been transmitted; ACK has been received Data byte has been transmitted; NOT ACK has been received Arbitration lost in SLA+W or data bytes Application Software Response Next Action Taken by TWI Hardware To/from TWDR To TWCRn Load data byte or 0 0 1 X Data byte will be transmitted and ACK or NOT ACK will be received No TWDR action or 1 0 1 X Repeated S
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Figure 23-12.
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Figure 23-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........ Device n R1 R2 SD A SCL A START condition is sent by writing to the TWI Control register (TWCRn) a value of the type TWCRn=1x10x10x: • TWCRn.TWEN must be written to '1' to enable the 2-wire Serial Interface • TWCRn.TWSTA must be written to '1' to transmit a START condition • TWCRn.TWINT must be cleared by writing a '1' to it.
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Table 23-4.
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Status Code (TWSRn) Prescaler Bits are 0 0x58 Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response Data byte has been received; NOT ACK has been returned Next Action Taken by TWI Hardware To/from TWD To TWCRn Read data byte 1 0 1 X Repeated START will be transmitted 0 1 1 X STOP condition will be transmitted and TWSTO Flag will be reset 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset ST
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23.7.3. Slave Transmitter Mode In the Slave Transmitter (ST) mode, a number of data bytes are transmitted to a Master Receiver, as in the figure below. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 23-15. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 SLAVE TRANSMITTER MASTER RECEIVER Device 3 ........
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AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note: The 2-wire Serial Interface Data Register (TWDRn) does not reflect the last byte present on the bus when waking up from these Sleep modes. Table 23-5.
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Status Code (TWSRb) Prescaler Bits are 0 0xC0 Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Data byte in TWDRn has been transmitted; Application SofTWARne Response Next Action Taken by TWI Hardware To/from TWDRn To TWCRn No TWDRn action 0 0 1 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 1 1 Switched to the not addressed Slave mode; STA STO TWINT TWEA NOT ACK has been received own SLA will be recognized; GCA will be recognized if
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Status Code (TWSRb) Prescaler Bits are 0 0xC8 Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Last data byte in TWDRn has been transmitted (TWEA = “0”); Application SofTWARne Response Next Action Taken by TWI Hardware To/from TWDRn To TWCRn No TWDRn action 0 0 1 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 1 1 Switched to the not addressed Slave mode; STA STO TWINT TWEA ACK has been received own SLA will be recognized; GCA will be
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Figure 23-16. Formats and States in the Slave Transmitter Mode Reception of the o wn sla ve address and one or more data b ytes S SLA R A DATA 0xA8 Arbitration lost as master and addressed as sla ve A DATA 0xB8 A P or S 0xC0 A 0xB0 Last data b yte tr ansmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S 0xC8 From master to sla ve DATA From slave to master 23.7.4.
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When TWARn and TWCRn have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address, if enabled) followed by the data direction bit. If the direction bit is '0' (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT Flag is set and a valid status code can be read from TWSR.
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Status Code Status of the 2-wire Serial (TWSR) Bus and 2-wire Serial Interface Hardware Prescaler Bits are 0 Application SofTWARne Response To/from TWDRn To TWCRn 0x80 Read data byte X 0 1 0 Data byte will be received and NOT ACK will be returned X 0 1 1 Data byte will be received and ACK will be returned 0 0 1 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 1 1 Switched to the not addressed Slave mode; Previously addressed with own SLA+W; data has b
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Status Code Status of the 2-wire Serial (TWSR) Bus and 2-wire Serial Interface Hardware Prescaler Bits are 0 Application SofTWARne Response To/from TWDRn To TWCRn 0x98 Read data byte 0 0 1 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 1 1 Switched to the not addressed Slave mode; Previously addressed with general call; STA STO TWINT TWEA data has been received; NOT ACK has been returned Next Action Taken by TWI Hardware own SLA will be recognized; GCA wi
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Status Code Status of the 2-wire Serial (TWSR) Bus and 2-wire Serial Interface Hardware Prescaler Bits are 0 Application SofTWARne Response To/from TWDRn To TWCRn 0xA0 No action 0 0 1 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 1 1 Switched to the not addressed Slave mode; A STOP condition or repeated START condition has been received while still addressed as Slave Next Action Taken by TWI Hardware STA STO TWINT TWEA own SLA will be recognized; GCA will
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Figure 23-18. Formats and States in the Slave Receiver Mode Reception of the o wn sla ve address and one or more data b ytes.
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Table 23-7. Miscellaneous States Status Code (TWSR) Prescaler Bits are 0 Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWDRn To TWCRn STA STO TWINT TWEA 0xF8 No relevant state information available; TWINT = “0” No TWDRn action No TWCRn action 0x00 Bus error due to an illegal START or STOP condition No TWDRn action 0 23.7.6.
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Figure 23-20. An Arbitration Example VCC Device 1 Device 2 Device 3 MASTER TRANSMITTER MASTER TRANSMITTER SLAVE RECEIVER ........ Device n R1 R2 SD A SCL Several different scenarios may arise during arbitration, as described below: • • • Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will know about the bus contention. Two or more masters are accessing the same Slave with different data or direction bit.
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Figure 23-21. Possible Status Codes Caused by Arbitration START SLA Data Arbitration lost in SLA Own Address / General Call received No STOP Arbitration lost in Data 38 TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free Yes Direction Write 68/78 Read B0 23.9.
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23.9.1. TWI Bit Rate Register Name: TWBR Offset: 0xB8 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TWBRn: TWI Bit Rate Register [n = 7:0] TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
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23.9.2. TWI Status Register Name: TWSR Offset: 0xB9 Reset: 0xF8 Property: - Bit 7 6 5 4 3 TWS7 TWS6 TWS5 TWS4 TWS3 2 1 0 Access R R R R R R R/W R/W Reset 1 1 1 1 1 0 0 0 TWPS[1:0] Bits 3, 4, 5, 6, 7 – TWS3, TWS4, TWS5, TWS6, TWS7: TWI Status Bit The TWS[7:3] reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes are described later in this section.
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23.9.3. TWI (Slave) Address Register The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multi master systems, TWAR must be set in masters which can be addressed as Slaves by other Masters. The LSB of TWAR is used to enable recognition of the general call address (0x00).
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23.9.4. TWI Data Register In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set.
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23.9.5. TWI Control Register The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.
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STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state. Bit 3 – TWWC: TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high. Bit 2 – TWEN: TWI Enable The TWEN bit enables TWI operation and activates the TWI interface.
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23.9.6. TWI (Slave) Address Mask Register Name: TWAMR Offset: 0xBD Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 0 R/W R/W R/W R/W R/W R/W R/W R 0 0 0 0 0 0 0 0 Bits 1, 2, 3, 4, 5, 6, 7 – TWAMn: TWI (Slave) Address The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI Address Register (TWAR).
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24. AC - Analog Comparator 24.1. Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
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Table 24-1. Analog Comparator Multiplexed Input 24.3.
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24.3.1. Analog Comparator Control and Status Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. Bits 1:0 – ACISn: Analog Comparator Interrupt Mode Select [n = 1:0] These bits determine which comparator events that trigger the Analog Comparator interrupt. Table 24-2. ACIS[1:0] Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle.
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24.3.2. Digital Input Disable Register 1 Name: DIDR1 Offset: 0x7F Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 Reserved5 Reserved4 Reserved3 Reserved2 Reserved1 Reserved0 AIN1D AIN0D Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 2, 3, 4, 5, 6, 7 – Reservedn Bits 0, 1 – AIN0D, AIN1D: AIN Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled.
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25. ADC - Analog to Digital Converter 25.1. Features • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-Linearity ±2 LSB Absolute Accuracy 13 - 260μs Conversion Time Up to 15kSPS at Maximum Resolution 8 Multiplexed Single Ended Input Channels Differential mode with selectable gain at 1x, 10x or 200x(1) Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 2.7V - VCC Differential ADC Voltage Range Selectable 2.56V or 1.
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writing to the REFSn bits in the ADMUX Register. The internal voltage reference must be decoupled by an external capacitor at the AREF pin to improve noise immunity. Figure 25-1. Analog to Digital Converter Block Schematic Operation ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS0 ADPS1 ADPS2 ADIF ADATE ADEN ADSC MUX1 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL.
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The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADC Left Adjust Result bit ADMUX.ADLAR. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH.
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Figure 25-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a '1' to ADCSRA.ADSC.
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is switched on by writing the ADC Enable bit ADCSRA.ADEN to '1'. The prescaler keeps running for as long as ADEN=1, and is continuously reset when ADEN=0. When initiating a single ended conversion by writing a '1' to the ADC Start Conversion bit (ADCSRA.ADSC), the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (i.e., ADCSRA.
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Figure 25-5. ADC Timing Diagram, Single Conversion One Conversion 1 Cycle Number 2 3 4 5 6 Next Conversion 7 8 9 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample and Hold Conversion Complete MUX and REFS Update MUX and REFS Update Figure 25-6.
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Table 25-1. ADC Conversion Time Condition Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 14.5 25 Normal conversions, single ended 1.5 13 Auto Triggered conversions 2 13.5 Normal conversions, differential 1.5/2.5 13/14 25.4.1. Differential Gain Channels When using differential gain channels, certain aspects of the conversion need to be taken into consideration. Note that the differential channels should not be used with an AREF < 2V.
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If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both the ADC Auto Trigger Enable and ADC Enable bits (ADCRSA.ADATE, ADCRSA.ADEN) are written to '1', an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings.
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The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. If differential channels are used, the selected reference should not be closer to AVCC than indicated in ADC Characteristics of Electrical Characteristics chapter. 25.6. ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals.
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Figure 25-8. Analog Input Circuitry IIH ADCn 1..100kΩ IIL CS/H= 14pF VCC/2 25.6.2. Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. 2. 3. 4. Keep analog signal paths as short as possible.
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Analog Ground Plane PA3 (ADC3) PA2 (ADC2) PA1 (ADC1) PA0 (ADC0) VCC GND Figure 25-9. ADC Power Connections PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) AREF 10μH PA7 (ADC7) AVCC 100nF GND PC7 25.6.3. Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs.
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Figure 25-10. Offset Error Output Code Ideal ADC Actual ADC Offset Error • VREF Input Voltage Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB. Figure 25-11.
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• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 25-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 • • 25.7. VREF Input Voltage Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
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Figure 25-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF /GAIN 0x3FF 0 VREF /GAIN Diffe re ntia l Input Volta ge (Volts ) 0x200 The table below shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is selected with a gain of GAIN and a reference voltage of VREF. Table 25-2. Correlation between Input Voltage and Output Codes VADCn Read code Corresponding Decimal Value VADCm + VREF/GAIN 0x1FF 511 VADCm + 0.999 VREF/GAIN 0x1FF 511 VADCm + 0.
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Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. 25.8.
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25.8.1. ADC Multiplexer Selection Register Name: ADMUX Offset: 0x7C Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:6 – REFSn: Reference Selection [n = 1:0] These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).
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Table 25-4.
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MUX[4:0] Single Ended Input Positive Differential Input 11110 1.
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25.8.2. ADC Control and Status Register A Name: ADCSRA Offset: 0x7A Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
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ADPS[2:0] Division Factor 010 4 011 8 100 16 101 32 110 64 111 128 Atmel ATmega644A [DATASHEET] Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016 321
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25.8.3. ADC Data Register Low and High Byte (ADLAR=0) The ADCL and ADCH register pair represents the 16-bit value, ADC Data Register. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. When an ADC conversion is complete, the result is found in these two registers.
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25.8.4. ADC Data Register Low and High Byte (ADLAR=1) The ADCL and ADCH register pair represents the 16-bit value, ADC Data Register. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. When an ADC conversion is complete, the result is found in these two registers.
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25.8.5. ADC Control and Status Register B Name: ADCSRB Offset: 0x7B Reset: 0x00 Property: - Bit 7 6 Access 2 1 0 ACME ADTS2 ADTS1 ADTS0 R/W R/W R/W R/W 0 0 0 0 Reset 5 4 3 Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator.
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25.8.6. Digital Input Disable Register 0 When the respective bits are written to logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7...0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
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26. JTAG Interface and On-chip Debug System 26.1. Features • • • • • • 26.2. JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the IEEE std. 1149.
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TAP – Test Access Port The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are: • • • • TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine. TCK: Test clock. JTAG operation is synchronous to TCK. TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). TDO: Test Data Out.
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Figure 26-2. TAP Controller State Diagram 1 Te s t-Logic-Re s e t 0 0 Run-Te s t/Idle 1 S e le ct-DR S ca n 1 S e le ct-IR S ca n 0 0 1 1 Ca pture -DR Ca pture -IR 0 0 S hift-DR S hift-IR 0 1 Exit1-DR 0 P a us e -DR 0 0 P a us e -IR 1 1 0 Exit2-DR Exit2-IR 1 1 Upda te -DR 26.4.
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• • • held low during input of the 3 LSBs in order to remain in the Shift-IR state. The MSB of the instruction is shifted in when this state is left by setting TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state.
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• • 2 Single Program Memory break points + 1 Program Memory break point with mask (“range break point”) 2 Single Program Memory break points + 1 Data Memory break point with mask (“range break point”) A debugger, like the Atmel Studio®, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in On-chip Debug Specific JTAG Instructions.
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The JTAG programming capability supports: • • • • Flash programming and verifying EEPROM programming and verifying Fuse programming and verifying Lock bit programming and verifying The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no back-door exists for reading out the content of a secured device.
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software may be in an undetermined state when exiting the test mode. Entering Reset, the outputs of any Port Pin will instantly enter the high impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued to make the shortest possible scan chain through the device. The device can be set in the Reset state either by pulling the external RESET pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register.
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Table 26-1. AVR JTAG Part Number Part Number JTAG Part Number ATmega644A 960A 26.11.2.3. Manufacturer ID The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is listed in the table below. Table 26-2. Manufacturer ID Manufacturer JTAG Manufacturer ID (Hex) ATMEL 0x01F 26.11.3. Reset Register The Reset Register is a Test Data Register used to reset the part.
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implemented, but all outputs with tri-state capability can be set in high-impedant state by using the AVR_RESET instruction, since the initial state for all port pins is tri-state. As a definition in this data sheet, the LSB is shifted in and out first for all Shift Registers. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which data register is selected as path between TDI and TDO for each instruction. 26.12.1.
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The active states are: • • Capture-DR: Loads a logic “0” into the Bypass Register. Shift-DR: The Bypass Register cell between TDI and TDO is shifted. 26.13. Boundary-scan Chain The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. 26.13.1.
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Figure 26-5. Boundary-scan Cell for Bi-directional Port Pin with Pull-Up Function.
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Figure 26-6.
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26.14. ATmega644A Boundary-scan Order The table below shows the Scan order between TDI and TDO when the Boundary-scan Chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A are scanned in the opposite bit order of the other ports.
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Bit Number Signal Name Module 39 PD0.Data Port D 38 PD0.Control 37 PD1.Data 36 PD1.Control 35 PD2.Data 34 PD2.Control 33 PD3.Data 32 PD3.Control 31 PD4.Data 30 PD4.Control 29 PD5.Data 28 PD5.Control 27 PD6.Data 26 PD6.Control 25 PD7.Data 24 PD7.Control 23 PC0.Data 22 PC0.Control 21 PC1.Data 20 PC1.Control 19 PC6.Data 18 PC6.Control 17 PC7.Data 16 PC7.
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Bit Number Signal Name Module 15 PA7.Data Port A 14 PA7.Control 13 PA6.Data 12 PA6.Control 11 PA5.Data 10 PA5.Control 9 PA4.Data 8 PA4.Control 7 PA3.Data 6 PA3.Control 5 PA2.Data 4 PA2.Control 3 PA1.Data 2 PA1.Control 1 PA0.Data 0 PA0.Control 26.15. Boundary-scan Description Language Files Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software.
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26.16.1. OCDR – On-chip Debug Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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26.16.2. MCU Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions.
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
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26.16.3. MCU Status Register To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used.
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27. BTLDR - Boot Loader Support – Read-While-Write Self-Programming 27.1. Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 1. A page is a section in the Flash consisting of several bytes (see Table. No. of Words in a Page and No.
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27.4. Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-Write (NRWW) section.
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Figure 27-1. Read-While-Write vs.
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Figure 27-2.
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Table 27-2. Boot Reset Fuse BOOTRST Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset, as described by the Boot Loader Parameters Note: '1' means unprogrammed, '0' means programmed. 27.6. Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two separate sets of Boot Lock bits which can be set independently.
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BLB1 Mode BLB12 BLB11 Protection 3 0 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. 4 0 1 LPM executing from the Application section is not allowed to read from the Boot Loader section.
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Figure 27-3. Addressing the Flash During SPM BIT 15 ZPAGEMSB ZPCMSB 1 0 0 Z - REGISTER PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: The different variables used in this figure are listed in the Related Links. 27.8. Self-Programming the Flash The program memory is updated in a page by page fashion.
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can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page. Please refer to Simple Assembly Code Example for a Boot Loader. 27.8.1. Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “0x0000011” to Store Program Memory Control and Status Register (SPMCSR) and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
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busy. During Self-Programming the Interrupt Vector table should be moved to the BLS as described in Watchdog Timer chapter, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the SPMCSR.RWWSB by writing the SPMCSR.RWWSRE. Please refer to Simple Assembly Code Example for a Boot Loader for an example. Related Links Watchdog System Reset on page 70 27.8.7.
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Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 When reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the SPMCSR.BLBSET and SPMCSR.SPMEN are set, the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Bit 7 6 5 4 3 2 1 0 Rd – – – – – EFB2 EFB1 EFB0 Fuse and Lock bits that are programmed read as '0'.
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27.8.11. Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
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.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words .org SMALLBOOTSTART Write_page: ; Page Erase ldi spmcrval, (1<
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Rdloop: lpm r0, Z+ ld r1, Y+ cpse r0, r1 jmp Error sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256 brne Rdloop ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
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ret 27.8.14. ATmega644A Boot Loader Parameters In the following tables, the parameters used in the description of the self programming are given. Table 27-7.
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Variable Corresponding Variable (1) Description PCPAGE PC[14:7] Z15:Z8 Program counter page address: Page select, for page erase and page write PCWORD PC[6:0] Program counter word address: Word select, for filling temporary buffer (must be zero during page write operation) Z7:Z1 Note: 1. Z0: should be zero for all SPM commands, byte select for the LPM instruction. See Addressing the Flash During Self-Programming for details about the use of Z-pointer during Self- Programming. 27.9.
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27.9.1. SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations. When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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Bit 3 – BLBSET: Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits and Memory Lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles.
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28. MEMPROG- Memory Programming 28.1. Program And Data Memory Lock Bits The devices provides Lock bits. These can be left unprogrammed ('1') or can be programmed ('0') to obtain the additional features listed in Table. Lock Bit Protection Modes in this section. The Lock bits can only be erased to “1” with the Chip Erase command. Table 28-1. Lock Bit Byte(1) Lock Bit Byte Bit No.
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Table 28-3. Lock Bit Protection - BLB0 Mode(1)(2). BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or Load Program Memory (LPM) instruction accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 3 0 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
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Extended Fuse Byte Bit No. Description Default Value – 5 – 0 – 4 – 0 - 3 - 0 BODLEVEL2 (1) 2 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL1 (1) 1 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL0 (1) 0 Brown-out Detector trigger level 1 (unprogrammed) Note: 1. Please refer to Table. BODLEVEL Fuse Coding in System and Reset Characteristics for BODLEVEL Fuse decoding. Table 28-6. Fuse High Byte. (0x99) High Fuse Byte Bit No.
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High Fuse Byte Bit No. Description Default Value EESAVE 3 EEPROM memory is preserved through the Chip Erase 1 (unprogrammed), EEPROM not reserved BODLEVEL2(4) 2 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL1(4) 1 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL0(4) 0 Brown-out Detector trigger level 1 (unprogrammed) Note: 1. Please refer to Alternate Functions of Port C in I/O-Ports chapter for description of RSTDISBL Fuse. 2.
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WDTCSR on page 75 System and Reset Characteristics on page 399 Clock characteristics on page 398 28.2.1. Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 28.3.
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Table 28-11. No. of Words in a Page and No. of Pages in the EEPROM 28.7. Device EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB ATmega644A 2Kbytes 8bytes EEA[2:0] 256 EEA[10:2] 10 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the device. Pulses are assumed to be at least 250ns unless otherwise noted. 28.7.1.
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Signal Name in Programming Mode Pin Name I/O Function WR PD3 I Write Pulse (Active low) BS1 PD4 I Byte Select 1 (“0” selects Low byte, “1” selects High byte) XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 PAGEL PD7 I Program memory and EEPROM Data Page Load BS2 PC2 I Byte Select 2 (“0” selects Low byte, “1” selects 2’nd High byte) DATA PB[7:0] I/O Bi-directional Data bus (Output when OE is low) Table 28-13. BS2 and BS1 encoding.
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Command Byte Command Executed 0010 0000 Write Lock bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM 28.8. Parallel Programming 28.8.1. Enter Programming Mode The following algorithm puts the device in Parallel (High-voltage) Programming mode: 1.
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28.8.3. Chip Erase The Chip Erase will erase the Flash, the SRAM and the EEPROM memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. Note: The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. Load Command “Chip Erase”: 28.8.4. 1. 2. Set XA1, XA0 to “10”. This enables command loading. Set BS1 to “0”. 3. 4. 5. 6.
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2. Give PAGEL a positive pulse. This latches the data bytes. (Please refer to the figure, Programming the Flash Waveforms, in this section for signal waveforms) Step F. Repeat B Through E Until the Entire Buffer Is Filled or Until All Data Within the Page Is Loaded While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in the following figure, Addressing the Flash Which is Organized in Pages, in this section.
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Figure 28-2. Addressing the Flash Which Is Organized in Pages PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: PCPAGE and PCWORD are listed in the table of No. of Words in a Page and No. of Pages in the Flash in Page Size section. Programming the Flash Waveforms F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR.
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into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (For details on Command, Address and Data loading, please refer to Programming the Flash): 1. 2. 3. 4. 5. Step A: Load Command “0001 0001”. Step G: Load Address High Byte (0x00 - 0xFF). Step B: Load Address Low Byte (0x00 - 0xFF). Step C: Load Data (0x00 - 0xFF). Step E: Latch data (give PAGEL a positive pulse). 6. 7.
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1. 2. 3. 4. 5. 28.8.8. Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (Please refer to Programming the Flash for details on Command and Data loading): 1. 2. 3. 28.8.9. Step A: Load Command “0000 0011”. Step G: Load Address High Byte (0x00 - 0xFF). Step B: Load Address Low Byte (0x00 - 0xFF). Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. Set OE to “1”. Step A: Load Command “0100 0000”. Step C: Load Data Low Byte.
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Figure 28-4. Programming the FUSES Waveforms Write Fuse Low byte A DATA 0x40 A C DATA XX Write Extended Fuse byte Write Fuse high byte 0x40 A C DATA XX 0x40 C DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 28.8.11. Programming the Lock Bits The algorithm for programming the Lock bits is as follows (Please refer to Programming the Flash for details on Command and Data loading): 1. 2. 3. Step A: Load Command “0010 0000”. Step C: Load Data Low Byte.
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Figure 28-5. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte 1 BS1 BS2 28.8.13. Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (Please refer to Programming the Flash for details on Command and Address loading): 1. 2. 3. 4. Step A: Load Command “0000 1000”. Step B: Load Address Low Byte (0x00 - 0x02). Set OE to “0”, and BS1 to “0”.
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Figure 28-6. Serial Programming and Verify +1.8 - 5.5V VCC +1.8 - 5.5V(2) MOSI AVCC MISO SCK EXTCLK RESET GND Note: 1. 2. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.
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To program and verify the device in the serial programming mode, the following sequence is recommended (See Serial Programming Instruction set in Table 28-19: 1. 2. 3. 4. 5. 6. 7. 8. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.
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28.9.3. Symbol Minimum Wait Delay tWD_ERASE 10.5ms tWD_FUSE 4.5ms Serial Programming Instruction Set This section describes the Instruction Set. Table 28-19.
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Instruction/Operation Instruction Format Byte 1 Byte 2 Byte 3 Byte 4 Write Fuse High bits 0xAC 0xA8 0x00 data byte in Write Extended Fuse Bits 0xAC 0xA4 0x00 data byte in Note: 1. Not all instructions are applicable for all parts. 2. a = address. 3. Bits are programmed ‘0’, unprogrammed ‘1’. 4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) . 5. Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6.
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28.9.4. SPI Serial Programming Characteristics Figure 28-8. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE 28.10. Programming Via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the Reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN fuse must be programmed.
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Figure 28-9. State Machine Sequence for Changing the Instruction Word 1 Te s t-Logic-Re s e t 0 0 Run-Te s t/Idle 1 S e le ct-DR S ca n 1 S e le ct-IR S ca n 0 0 1 1 Ca pture -DR Ca pture -IR 0 0 S hift-DR S hift-IR 0 1 Exit1-DR 1 Exit1-IR 0 0 Pa us e -DR 0 0 Pa us e -IR 1 1 0 Exit2-DR Exit2-IR 1 1 Upda te -DR 1 0 1 1 0 1 Upda te -IR 0 1 0 28.10.2.
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28.10.3. PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-bit Programming Enable Register is selected as data register. The active states are the following: • • Shift-DR: the programming enable signature is shifted into the data register. Update-DR: the programming enable signature is compared to the correct value, and Programming mode is entered if the signature is valid. 28.10.4.
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• • • • Programming Enable Register Programming Command Register Virtual Flash Page Load Register Virtual Flash Page Read Register 28.10.8. Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering programming mode. A high value in the Reset Register corresponds to pulling the external Reset low. The part is reset as long as there is a high value present in the Reset Register.
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Figure 28-11. Programming Command Register TDI S T R O B E S Fla s h EEP ROM Fus e s Lock Bits A D D R E S S / D A T A TDO Table 28-20. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence 1a. Chip erase 0100011_10000000 0110001_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 0110011_10000000 xxxxxxx_xxxxxxxx 0110011_10000000 xxxxxxx_xxxxxxxx 1b.
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Instruction TDI sequence TDO sequence Notes 2g. Write Flash Page 0110111_00000000 0110101_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 2h. Poll for Page Write complete 0110111_00000000 xxxxxox_xxxxxxxx 3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 3d.
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Instruction TDI sequence TDO sequence Notes 6c. Write Fuse Extended byte 0111011_00000000 0111001_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 0111011_00000000 xxxxxxx_xxxxxxxx 0111011_00000000 xxxxxxx_xxxxxxxx 6d. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 6e. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6f.
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Instruction TDI sequence TDO sequence Notes 8f. Read Fuses and Lock bits 0111010_00000000 0111110_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo (5) fuse ext. byte 0110010_00000000 xxxxxxx_oooooooo fuse high byte 0110110_00000000 xxxxxxx_oooooooo fuse low byte 0110111_00000000 xxxxxxx_oooooooo lock bits 9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 9c.
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Figure 28-12. State Machine Sequence for Changing/Reading the Data Word 1 Te s t-Logic-Re s e t 0 0 Run-Te s t/Idle 1 S e le ct-DR S ca n 1 S e le ct-IR S ca n 0 0 1 1 Ca pture -DR Ca pture -IR 0 0 S hift-DR S hift-IR 0 1 Exit1-DR 1 Exit1-IR 0 0 Pa us e -DR 0 0 Pa us e -IR 1 1 0 Exit2-DR Exit2-IR 1 1 Upda te -DR 1 0 1 1 0 1 Upda te -IR 0 1 0 28.10.11.
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Figure 28-13. Virtual Flash Page Load Register S TROBES TDI S ta te ma chine ADDRES S Fla s h EEP ROM Fus e s Lock Bits D A T A TDO 28.10.12. Virtual Flash Page Read Register The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte by byte.
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Figure 28-14. Virtual Flash Page Read Register S TROBES TDI S ta te ma chine ADDRES S Fla s h EEP ROM Fus e s Lock Bits D A T A TDO 28.10.13. Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 28-20. 28.10.14. Entering Programming Mode 1. 2. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. 28.10.15. Leaving Programming Mode 1. 2. 3. 4.
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4. 5. 6. 7. 8. 9. Load address low byte using programming instruction 2c. Load data using programming instructions 2d, 2e and 2f. Repeat steps 4 and 5 for all instruction words in the page. Write the page using programming instruction 2g. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to table Parallel Programming Characteristics, VCC = 5V ±10% in chapter Parallel Programming Characteristics). Repeat steps 3 to 7 until all data have been programmed.
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1. 2. 3. 4. 5. 6. 7. 8. 9. Enter JTAG instruction PROG_COMMANDS. Enable EEPROM write using programming instruction 4a. Load address high byte using programming instruction 4b. Load address low byte using programming instruction 4c. Load data using programming instructions 4d and 4e. Repeat steps 4 and 5 for all data bytes in the page. Write the data using programming instruction 4f.
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3. 4. 5. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. Write Lock bits using programming instruction 7c. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to table Parallel Programming Characteristics, VCC = 5V ±10% in chapter Parallel Programming Characteristics). 28.10.23. Reading the Fuses and Lock Bits 1. 2. 3. Enter JTAG instruction PROG_COMMANDS.
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29. Electrical Characteristics 29.1. Absolute Maximum Ratings Table 29-1. Absolute Maximum Ratings Operating Temperature -55°C to +125°C Storage Temperature -65°C to +150°C Voltage on any Pin except RESET with respect to Ground -0.5V to VCC+0.5V Voltage on RESET with respect to Ground -0.5V to +13.0V Maximum Operating Voltage 6.0V DC Current per I/O Pin 40.0mA DC Current VCC and GND Pins 200.
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Symbol Parameter VOL Output Low Voltage(4) except RESET pin Condition Min. Typ. IOL = 20mA, Max. Units 0.9 V VCC = 5V 0.6 IOL = 10mA, VCC = 3V VOH Output HighVoltage(3) except Reset pin 4.2 IOH = -20mA, V VCC = 5V 2.3 IOH = -10mA, VCC = 3V Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1 μA IIH Input Leakage Current I/O Pin VCC = 5.
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4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 4.1. The sum of all IOL, for ports PB0-PB7, XTAL2, PD0-PD7 should not exceed 100mA. 4.2. The sum of all IOH, for ports PA0-PA3, PC0-PC7 should not exceed 100mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.
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Figure 29-1. Maximum Frequency vs. VCC 20MHz 10MHz Safe Operating Area 4MHz 1.8V 29.4. 2.7V 4.5V 5.5V Clock Characteristics Related Links Calibrated Internal RC Oscillator on page 48 29.4.1. Clock characteristics Table 29-4. Calibration accuracy of internal RC oscillator. 29.4.2. Frequency VCC Temperature Calibration accuracy Factory calibration 8.0MHz 3V 25°C ±10% User calibration 7.3 - 8.1MHz 1.8 - 5.5V -40°C - 85°C ±1% External Clock Drive Waveforms Figure 29-2.
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Symbol Parameter 29.5. VCC= 1.8 - 5.5V VCC= 2.7 - 5.5V VCC= 4.5 - 5.5V Units Min. Max. Min. Max. Min. Max. tCLCH Rise Time - 2.0 - 1.6 - 0.5 μs tCHCL Fall Time - 2.0 - 1.6 - 0.5 μs ΔtCLCL Change in period from one clock cycle to the next - 2 - 2 - 2 % System and Reset Characteristics Table 29-6. Reset, Brown-out and Internal Voltage Characteristics Symbol Parameter Min. Typ Max Units Power-on Reset Threshold Voltage (rising) 1.1 1.4 1.
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Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 and 101 . 29.6. External interrupts characteristics Table 29-8. Asynchronous external interrupt characteristics. 29.7.
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Note: 1. In SPI Programming mode the minimum SCK high/low period is: • • 2 tCLCL for fCK < 12MHz 3 tCLCL for fCK > 12MHz Figure 29-3. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) MSB 8 ... LSB Figure 29-4. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 29.8. MSB 17 .
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Table 29-10. Two-wire Serial Bus Requirements Symbol Parameter Condition Min. Max Units V VIL Input Low-voltage -0.5 0.3 VCC VIH Input High-voltage 0.7 VCC VCC + 0.5 V Vhys(1) Hysteresis of Schmitt Trigger Inputs 0.05 VCC(2) – V VOL(1) Output Low-voltage 0 0.
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Symbol Parameter Condition Min. Max Units tBUF fSCL ≤ 100kHz 4.7 – μs fSCL > 100kHz 1.3 – μs Bus free time between a STOP and START condition Note: 1. This parameter is characterized and not 100% tested. 2. Required only for fSCL > 100kHz. 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency. 5. This requirement applies to all 2-wire Serial Interface operation. Other devices connected to the 2wire Serial Bus need only obey the general fSCL requirement. Figure 29-5.
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Condition Min.(1) Typ Max Units Offset Error VREF = 4V, VCC = 4V, ADC clock = 200kHz - -1.5 - LSB Conversion Time Free Running Conversion 13 - 260 μs Clock Frequency 50 - 1000 kHz AVCC(1) Analog Supply Voltage VCC - 0.3 - VCC + 0.3 V VREF Reference Voltage 1.0 - AVCC V VIN Input Voltage GND - VREF V Input Bandwidth - 38.5 - kHz VINT Internal Voltage Reference 1.0 1.1 1.
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Symbol Min(1) Typ(1) Max(1) Units Integral Non- Gain = 1×, linearity (INL) VCC = 5V, VREF = 4V ADC clock = 200 kHz - 2.25 - LSB Gain = 10×, VCC = 5V, VREF = 4V ADC clock = 200 kHz - 4.25 - Gain = 200×, VCC = 5V, VREF = 4V ADC clock = 200 kHz 11.5 - Gain = 1×, VCC = 5V, VREF = 4V ADC clock = 200 kHz - 0.75 - Gain = 10×, VCC = 5V, VREF = 4V ADC clock = 200 kHz - 0.75 - Gain = 200×, VCC = 5V, VREF = 4V ADC clock = 200 kHz 9.
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Symbol Parameter Condition Min(1) Typ(1) Max(1) Units Gain = 1×, VCC = 5V, VREF = 4V ADC clock = 200 kHz - 1 - LSB Gain = 10×, VCC = 5V, VREF = 4V ADC clock = 200 kHz - 1.25 - 2.5 - Gain = 200×, VCC = 5V, VREF = 4V ADC clock = 200 kHz Conversion Time 13 - 260 μs Clock Frequency 50 - 1000 kHz AVCC Analog Supply Voltage VCC - 0.3 - VCC + 0.3 V VREF Reference Voltage 2.0 - AVCC - 0.
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1. Values are guidelines only. 29.10. Parallel Programming Characteristics Table 29-13. Parallel programming characteristics, VCC = 5V ±10%. Symbol Parameter Min. Typ. Max. Units VPP Programming Enable Voltage 11.5 - 12.
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Figure 29-6. Parallel programming timing, including some general timing requirements. tXLWL tXHXL XTAL1 tDVXH Da ta & Contol (DATA, XA0/1, BS 1, BS 2) tXLDX tP LBX t BVWL tBVP H P AGEL tWLBX tP HP L tWLWH WR tP LWL WLRL RDY/BS Y tWLRH Figure 29-7. Parallel programming timing, loading sequence with timing requirements .
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30. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off.
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Figure 30-2. Active Supply Current vs. Frequency (1 - 20MHz) ICC (mA) 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Fre que ncy (MHz) Figure 30-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 7 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 1.4 85 °C 25 °C -40 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.
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Figure 30-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.22 -40 °C 25 °C 85 °C 0.2 0.18 ICC (mA) 0.16 0.14 0.12 0.1 0.08 0.06 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 30-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.24 5.5 V 0.2 5.0 V 4.5 V 4.0 V 0.16 ICC (mA) 30.2. 3.3 V 2.7 V 0.12 0.08 1.8 V 0.04 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 30-7. Idle Supply Current vs. Frequency (1 - 20MHz) 3.0 5.5V 5.0V 2.5 4.5V ICC (mA) 2.0 1.5 4.0V 1.0 3.3V 2.7V 0.5 1.8V 0.0 0 2 4 6 8 10 12 14 16 18 20 Fre que ncy (MHz) Figure 30-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 1.4 85 °C 25 °C -40 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 0.35 85 °C 25 °C -40 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.
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Figure 30-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.12 -40 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.3. Supply Current of I/O Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” for details.
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PRR bit Additional Current consumption compared to Active with external clock (See Figure 30-1 and Figure 30-2) Additional Current consumption compared to Idle with external clock (See Figure 30-6 and Figure 30-7) PRTIM2 3.3% 16.3% PRTIM1 1.9% 9.1% PRTIM0 0.9% 4.3% PRADC 3.65% 17.9% PRSPI 2.5% 12.4% It is possible to calculate the typical current consumption based on the numbers from Table 30-2 for other VCC and frequency settings than listed in Table 30-1.
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Figure 30-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 9 85 °C -40 °C 8 25 °C ICC (uA) 7 6 5 4 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply Current Figure 30-13. Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz crystal oscillator running) 2.5 85°C 2.0 1.5 Icc [µA] 30.5. 1.0 0.5 25°C -40°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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30.6. Standby Supply Current Figure 30-14. Standby Supply Current vs. VCC (Watchdog Timer Disabled) 0.16 6MHz_re s 6MHz_xta l 0.14 4MHz_re s 0.12 4MHz_xta l ICC (mA) 0.1 2MHz_re s 2MHz_xta l 1MHz_re s 450kHz_re s 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-Up Figure 30-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 35 IOP(uA) 30.7. 30 25 20 15 10 25oC 85oC -40oC 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 30-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP(uA) 50 40 30 20 25oC 85oC -40oC 10 0 0 0.5 1 1.5 2 2.5 3V VOP(V) Figure 30-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 5.1 5 4.9 VOH(V) 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.3 0 4 8 12 16 20 IOH(mA) Figure 30-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRESET(uA) 25 20 15 10 25oC -40oC 85oC 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.
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Figure 30-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET(uA) 40 30 20 10 25oC -40oC 85oC 0 0 0.5 1 1.5 2 2.5 3V VRESET(V) Figure 30-20. Reset Pull-up Resistor Current vs.
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Pin Driver Strength Figure 30-21. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 0.9 85 °C 0.8 0.7 25 °C VOL (V) 0.6 -40 °C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOH(mA) Figure 30-22. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 85 °C 0.5 25 °C 0.4 VOL (V) 30.8. -40 °C 0.3 0.2 0.
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Figure 30-23. I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.5 3 Curre nt (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH(mA) Figure 30-24. I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5.1 5 Curre nt (V) 4.9 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.
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Pin Threshold and Hysteresis Figure 30-25. I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 3 85 °C -40 °C 25 °C Thre s hold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-26. I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 2.5 -40 °C 85 °C 25 °C 2 Thre s hold (V) 30.9. 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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Figure 30-27. I/O Pin Input Hysteresis vs. VCC 0.6 25 °C 85 °C -40 °C Input Hys te re s is (mV) 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-28. Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 2.5 -40 °C 85 °C Thre s hold (V) 2 25 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-29. Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 2.5 -40 °C 85 °C Thre s hold (V) 2 25 °C 1.5 1 0.5 0 1.5 2 2.
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Figure 30-30. Reset Pin Input Hysteresis vs. VCC 0.7 Input Hys te re s is (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.10. BOD Threshold Figure 30-31. BOD Threshold vs. Temperature (VCC = 4.3V) 4.35 Rising Vcc Thre s hold (V) 4.32 4.29 Falling Vcc 4.26 4.23 4.
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Figure 30-32. BOD Threshold vs. Temperature (VCC = 2.7V) 2.77 2.75 Rising Vcc Thre s hold (V) 2.73 2.71 2.69 Falling Vcc 2.67 2.65 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 60 70 80 90 100 Temperature (C) Figure 30-33. BOD Threshold vs. Temperature (VCC = 1.8V) 1.84 1.83 Thre s hold (V) 1.82 Rising Vcc 1.81 1.8 1.79 Falling Vcc 1.78 1.77 1.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 Temperature (C) Figure 30-34. Calibrated Bandgap Voltage vs. VCC 1.
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Figure 30-35. Calibrated Bandgap Voltage vs. Temperature 1.087 1.083 1.8V 3.6V 2.7V 4.5V 1.081 5.5V Ba ndga p Volta ge (V) 1.085 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) 30.11. Internal Oscillator Speed Figure 30-36. Watchdog Oscillator Frequency vs. Temperature 119 118 117 116 F RC (kHz) 115 114 113 2.1 V 112 2.7 3.3 4.0 5.
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Figure 30-37. Watchdog Oscillator Frequency vs. VCC 119 118 117 -40oC 116 F RC (kHz) 115 25oC 114 113 112 111 110 85oC 109 108 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-38. Calibrated 8MHz RC Oscillator vs. VCC 8.4 85oC 8.2 25oC F RC (MHz) 8 -40oC 7.8 7.6 7.4 7.2 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-39. Calibrated 8MHz RC Oscillator vs. Temperature 8.4 5.0 V 8.3 3.0 V F RC (MHz) 8.2 8.1 8 7.9 7.8 7.7 7.
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Figure 30-40. Calibrated 8MHz RC Oscillator vs. OSCCAL Value 16 85 °C 25 °C -40 °C 14 F RC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OS CCAL (X1) 30.12. Current Consumption of Peripheral Units Figure 30-41. ADC Current vs. VCC (AREF = AVCC) 250 25 °C 85 °C -40 °C ICC (uA) 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.
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Figure 30-42. Analog Comparator Current vs. VCC 90 -40oC 80 25oC 85oC 70 ICC (uA) 60 50 40 30 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-43. AREF External Reference Current vs. VCC 200 25oC 85oC -40oC ICC (uA) 160 120 80 40 0 1.5 2 2.5 3 3.5 CC 4 4.5 5 5.5V (V) Figure 30-44. Brownout Detector Current vs. VCC 24 85oC 22 25oC -40oC ICC (uA) 20 18 16 14 12 2 2.5 3 3.5 4 4.5 5 5.
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Figure 30-45. Programming Current vs. VCC 16 -40 °C 14 12 ICC (mA) 10 25 °C 8 85 °C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-46. Watchdog Timer Current vs. VCC 9 8 -40oC 7 25oC 85oC ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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30.13. Current Consumption in Reset and Reset Pulse Width Figure 30-47. Reset supply current vs. Low Frequency (0.1 - 1.0Mhz) 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 30-48. Reset supply current vs. Frequency (1 - 20Mhz) 2 5.5V 1.75 5.0V 1.5 4.5V ICC (mA) 1.25 1 4.0V 0.75 3.3V 0.5 2.7V 0.25 1.
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Figure 30-49. Minimum Reset Pulsewidth vs. VCC 1800 1600 P uls e width (ns ) 1400 1200 1000 800 600 85 °C 25 °C -40 °C 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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31. Register Summary Offset Name Bit Pos.
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Offset Name 0x52 Reserved Bit Pos. 0x53 SMCR 7:0 0x54 MCUSR 7:0 0x55 MCUCR 7:0 JTD 0x56 Reserved 0x57 SPMCSR 7:0 SPMIE RWWSB SIGRD RWWSRE BLBSET 7:0 RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 7:0 SP7 SP6 SP5 JTRF SM2 SM1 SM0 SE WDRF BORF EXTRF PORF IVSEL IVCE PGWRT PGERS SPMEN RAMPZ2 RAMPZ1 RAMPZ0 PUD 0x58 ...
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Offset Name Bit Pos. 0x80 TCCR1A 7:0 COM1 COM1 0x81 TCCR1B 7:0 ICNC1 ICES1 0x82 TCCR1C 7:0 FOC1A FOC1B COM1 COM1 WGM13 WGM12 0x83 Reserved 0x84 TCNT1L and 7:0 TCNT1[7:0] 0x85 TCNT1H 15:8 TCNT1[15:8] 0x86 0x87 ICR1L and ICR1H 7:0 ICR1[7:0] 15:8 ICR1[15:8] 0x88 OCR1AL and 7:0 OCR1A[7:0] 0x89 OCR1AH 15:8 OCR1A[15:8] 0x8A OCR1BL and 7:0 OCR1B[7:0] 0x8B OCR1BH 15:8 OCR1B[15:8] CS12 WGM11 WGM10 CS11 CS10 WGM21 WGM20 0x8C ...
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Offset Name Bit Pos.
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32. Instruction Set Summary Table 31-1.
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Mnemonic Operands ICALL Description Indirect Call to (Z) Op Flags #Clocks None 3 / 4(1) None 4(1) PC(15:0) ← Z PC(21:16) ← 0 PC(15:0) ← Z PC(21:16) ← EIND call Subroutine PC ← k None 4 / 5(1) RET Subroutine Return PC ← STACK None 4 / 5(1) RETI Interrupt Return PC ← STACK I 4 / 5(1) if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 EICALL CALL Extended Indirect Call to (Z) k CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI
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Mnemonic Operands Description LDS Rd, k Load Direct from data space Rd ← LD Rd, X Load Indirect Rd LD Rd, X+ Load Indirect and Post-Increment LD Rd, -X Load Indirect and Pre-Decrement Op Flags #Clocks (k) None 2(1) ← (X) None 2(1) Rd ← (X) None 2(1) X ← X+1 X ← X-1 None 2(1) Rd ← (X) LD Rd, Y Load Indirect Rd ← (Y) None 2(1) LD Rd, Y+ Load Indirect and Post-Increment Rd ← (Y) None 2(1) Y ← Y+1 Y ← Y-1 None 2(1) Rd ← (Y) LD Rd, -Y Load
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Mnemonic Operands Description ELPM Rd, Z+ Extended Load Program Memory and Post-Increment SPM SPM Z+ (RAMPZ:Z) + 1 Store Program Memory (RAMPZ:Z) ← R1:R0 None (4) Store Program Memory and PostIncrement by 2 (RAMPZ:Z) ← R1:R0 None (4) Z ← Z+2 Rd ← I/O(A) None 1 I/O(A) ← Rr None 1 STACK ← Rr None 2 Rd ← STACK None 2 None N/A None N/A None N/A None N/A Flags #Clocks A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd Pop Register from Sta
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Mnemonic Operands Description Op Flags #Clocks CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z 1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S 1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Two’s Complement Overflow V ← 1 V 1 CLV Clear Two’s Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T 1 CLT Clear T in SREG T ← 0
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33. Packaging Information 33.1. 40-pin PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). SYMBOL MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.
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33.2. 44-pin TQFP P IN 1 IDENTIFIER P IN 1 B e E1 E A1 A2 D1 D C 0°~7° L A COMMON DIMENS IONS (Unit of Me a s ure = mm) Note s : 1. This pa cka ge conforms to J EDEC re fe re nce MS -026, Va ria tion ACB. 2. Dime ns ions D1 a nd E1 do not include mold protrus ion. Allowa ble protrus ion is 0.25mm pe r s ide . Dime ns ions D1 a nd E1 a re ma ximum pla s tic body s ize dime ns ions including mold mis ma tch. 3. Le a d copla na rity is 0.10mm ma ximum. S YMBOL MIN NOM MAX A – – 1.
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33.3. 44-pin VQFN D Marked Pin# 1 I D E SE ATING PLANE A1 TOP VIEW A3 A K L Pin #1 Co rne r D2 1 2 3 Option A SIDE VIEW Pin #1 Triangl e COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 SYMBOL E2 Option B K Option C b e Pin #1 Cham fe r (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW A3 0.20 REF b 0.18 0.23 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note : JEDEC Standard MO-220, Fig .
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34. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 34.1. Rev. C – 10/2016 • 34.2. Rev. B – 08/2016 • • 34.3. BTLDR - Boot Loader Support – Read-While-Write Self-Programming: Added information to the Simple Assembly Code Example for a Boot Loader. Pinout: Updated PDIP pinout, XTAL2 is connected to pin 12 and XTAL1 to pin 13.
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35. Errata 35.1. Rev. F No known errata.
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Atmel Corporation © 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com 2016 Atmel Corporation. / Rev.: Atmel-42716C-ATmega644A_Datasheet_Complete-10/2016 ® ® ® Atmel , Atmel logo and combinations thereof, Enabling Unlimited Possibilities , AVR , and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others.