Datasheet

363
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549Q–AVR–02/2014
6. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/f
SCL
- 2/f
CK
),
thus f
CK
must be greater than 6MHz for the low time requirement to be strictly met at f
SCL
= 100kHz.
7. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/f
SCL
- 2/f
CK
),
thus the low time requirement will not be strictly met for f
SCL
> 308kHz when f
CK
= 8MHz. Still,
ATmega640/1280/1281/2560/2561 devices connected to the bus may communicate at full speed (400kHz) with
other ATmega640/1280/1281/2560/2561 devices, as well as any other device with a proper t
LOW
acceptance
margin.
Figure 31-6. 2-wire Serial Bus Timing
31.7 SPI Timing Characteristics
See Figure 31-7 and Figure 31-8 on page 364 for details.
Note: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
CLCL
for f
CK
< 12MHz
- 3 t
CLCL
for f
CK
> 12MHz
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r
Table 31-8. SPI Timing Parameters
Description Mode Min. Typ. Max.
1 SCK period Master See Table 21-5 on page 198
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • t
sck
7 SCK to out Master 10
8 SCK to out high Master 10
9SS
low to out Slave 15
10 SCK period Slave 4 • t
ck
11 SCK high/low
(1)
Slave 2 • t
ck
12 Rise/Fall time Slave 1600
13 Setup Slave 10
14 Hold Slave t
ck
15 SCK to out Slave 15
16 SCK to SS
high Slave 20
17 SS high to tri-state Slave 10
18 SS
low to SCK Slave 20